[5] | 1 | /* |
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| 2 | ----------------------------------------------------------------------------- |
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| 3 | This source file is part of OGRE |
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| 4 | (Object-oriented Graphics Rendering Engine) |
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| 5 | For the latest info, see http://www.ogre3d.org/ |
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| 6 | |
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| 7 | Copyright (c) 2000-2006 Torus Knot Software Ltd |
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| 8 | Also see acknowledgements in Readme.html |
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| 9 | |
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| 10 | This program is free software; you can redistribute it and/or modify it under |
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| 11 | the terms of the GNU Lesser General Public License as published by the Free Software |
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| 12 | Foundation; either version 2 of the License, or (at your option) any later |
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| 13 | version. |
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| 14 | |
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| 15 | This program is distributed in the hope that it will be useful, but WITHOUT |
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| 16 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS |
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| 17 | FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details. |
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| 18 | |
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| 19 | You should have received a copy of the GNU Lesser General Public License along with |
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| 20 | this program; if not, write to the Free Software Foundation, Inc., 59 Temple |
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| 21 | Place - Suite 330, Boston, MA 02111-1307, USA, or go to |
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| 22 | http://www.gnu.org/copyleft/lesser.txt. |
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| 23 | |
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| 24 | You may alternatively use this source under the terms of a specific version of |
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| 25 | the OGRE Unrestricted License provided you have obtained such a license from |
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| 26 | Torus Knot Software Ltd. |
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| 27 | ----------------------------------------------------------------------------- |
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| 28 | */ |
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| 29 | |
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| 30 | |
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| 31 | //--------------------------------------------------------------------------- |
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| 32 | #include "ps_1_4.h" |
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| 33 | |
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| 34 | //--------------------------------------------------------------------------- |
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| 35 | |
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| 36 | /* ********************* START OF PS_1_4 CLASS STATIC DATA ********************************* */ |
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| 37 | |
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| 38 | |
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| 39 | // library of built in symbol types |
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| 40 | |
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| 41 | bool PS_1_4::LibInitialized = false; |
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| 42 | |
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| 43 | #define SYMSTART { |
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| 44 | #define SYMDEF ,0,0,0,0},{ |
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| 45 | #define SYMEND ,0,0,0,0} |
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| 46 | |
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| 47 | PS_1_4::SymbolDef PS_1_4::PS_1_4_SymbolTypeLib[] = { |
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| 48 | // pixel shader versions supported |
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| 49 | { sid_PS_1_4, GL_NONE, ckp_PS_BASE, ckp_PS_1_4, 0, 0, 0 }, |
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| 50 | { sid_PS_1_1, GL_NONE, ckp_PS_BASE, ckp_PS_1_1, 0, 0, 0 }, |
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| 51 | { sid_PS_1_2, GL_NONE, ckp_PS_BASE, ckp_PS_1_2 + ckp_PS_1_1, 0, 0, 0 }, |
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| 52 | { sid_PS_1_3, GL_NONE, ckp_PS_BASE, ckp_PS_1_3 + ckp_PS_1_2 + ckp_PS_1_1, 0, 0, 0 }, |
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| 53 | |
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| 54 | // PS_BASE |
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| 55 | |
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| 56 | // constants |
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| 57 | SYMSTART sid_C0, GL_CON_0_ATI, ckp_PS_BASE |
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| 58 | SYMDEF sid_C1, GL_CON_1_ATI, ckp_PS_BASE |
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| 59 | SYMDEF sid_C2, GL_CON_2_ATI, ckp_PS_BASE |
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| 60 | SYMDEF sid_C3, GL_CON_3_ATI, ckp_PS_BASE |
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| 61 | SYMDEF sid_C4, GL_CON_4_ATI, ckp_PS_BASE |
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| 62 | SYMDEF sid_C5, GL_CON_5_ATI, ckp_PS_BASE |
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| 63 | SYMDEF sid_C6, GL_CON_6_ATI, ckp_PS_BASE |
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| 64 | SYMDEF sid_C7, GL_CON_7_ATI, ckp_PS_BASE |
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| 65 | |
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| 66 | // colour |
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| 67 | SYMDEF sid_V0, GL_PRIMARY_COLOR_ARB, ckp_PS_BASE |
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| 68 | SYMDEF sid_V1, GL_SECONDARY_INTERPOLATOR_ATI, ckp_PS_BASE |
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| 69 | |
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| 70 | // instruction ops |
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| 71 | SYMDEF sid_ADD, GL_ADD_ATI, ckp_PS_BASE |
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| 72 | SYMDEF sid_SUB, GL_SUB_ATI, ckp_PS_BASE |
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| 73 | SYMDEF sid_MUL, GL_MUL_ATI, ckp_PS_BASE |
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| 74 | SYMDEF sid_MAD, GL_MAD_ATI, ckp_PS_BASE |
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| 75 | SYMDEF sid_LRP, GL_LERP_ATI, ckp_PS_BASE |
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| 76 | SYMDEF sid_MOV, GL_MOV_ATI, ckp_PS_BASE |
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| 77 | SYMDEF sid_CMP, GL_CND0_ATI, ckp_PS_BASE |
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| 78 | SYMDEF sid_CND, GL_CND_ATI, ckp_PS_BASE |
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| 79 | SYMDEF sid_DP3, GL_DOT3_ATI, ckp_PS_BASE |
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| 80 | SYMDEF sid_DP4, GL_DOT4_ATI, ckp_PS_BASE |
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| 81 | |
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| 82 | SYMDEF sid_DEF, GL_NONE, ckp_PS_BASE |
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| 83 | |
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| 84 | // Masks |
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| 85 | SYMDEF sid_R, GL_RED_BIT_ATI, ckp_PS_1_4 |
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| 86 | SYMDEF sid_RA, GL_RED_BIT_ATI | ALPHA_BIT, ckp_PS_1_4 |
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| 87 | SYMDEF sid_G, GL_GREEN_BIT_ATI, ckp_PS_1_4 |
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| 88 | SYMDEF sid_GA, GL_GREEN_BIT_ATI | ALPHA_BIT, ckp_PS_1_4 |
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| 89 | SYMDEF sid_B, GL_BLUE_BIT_ATI, ckp_PS_1_4 |
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| 90 | SYMDEF sid_BA, GL_BLUE_BIT_ATI | ALPHA_BIT, ckp_PS_1_4 |
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| 91 | SYMDEF sid_A, ALPHA_BIT, ckp_PS_BASE |
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| 92 | SYMDEF sid_RGBA, RGB_BITS | ALPHA_BIT, ckp_PS_BASE |
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| 93 | SYMDEF sid_RGB, RGB_BITS, ckp_PS_BASE |
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| 94 | SYMDEF sid_RG, GL_RED_BIT_ATI | GL_GREEN_BIT_ATI, ckp_PS_1_4 |
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| 95 | SYMDEF sid_RGA, GL_RED_BIT_ATI | GL_GREEN_BIT_ATI | ALPHA_BIT, ckp_PS_1_4 |
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| 96 | SYMDEF sid_RB, GL_RED_BIT_ATI | GL_BLUE_BIT_ATI, ckp_PS_1_4 |
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| 97 | SYMDEF sid_RBA, GL_RED_BIT_ATI | GL_BLUE_BIT_ATI | ALPHA_BIT, ckp_PS_1_4 |
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| 98 | SYMDEF sid_GB, GL_GREEN_BIT_ATI | GL_BLUE_BIT_ATI, ckp_PS_1_4 |
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| 99 | SYMDEF sid_GBA, GL_GREEN_BIT_ATI | GL_BLUE_BIT_ATI | ALPHA_BIT, ckp_PS_1_4 |
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| 100 | |
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| 101 | // Rep |
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| 102 | SYMDEF sid_RRRR, GL_RED, ckp_PS_1_4 |
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| 103 | SYMDEF sid_GGGG, GL_GREEN, ckp_PS_1_4 |
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| 104 | SYMDEF sid_BBBB, GL_BLUE, ckp_PS_BASE |
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| 105 | SYMDEF sid_AAAA, GL_ALPHA, ckp_PS_BASE |
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| 106 | |
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| 107 | |
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| 108 | // modifiers |
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| 109 | SYMDEF sid_X2, GL_2X_BIT_ATI, ckp_PS_BASE |
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| 110 | SYMDEF sid_X4, GL_4X_BIT_ATI, ckp_PS_BASE |
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| 111 | SYMDEF sid_D2, GL_HALF_BIT_ATI, ckp_PS_BASE |
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| 112 | SYMDEF sid_SAT, GL_SATURATE_BIT_ATI, ckp_PS_BASE |
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| 113 | |
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| 114 | // argument modifiers |
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| 115 | SYMDEF sid_BIAS, GL_BIAS_BIT_ATI, ckp_PS_BASE |
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| 116 | SYMDEF sid_INVERT, GL_COMP_BIT_ATI, ckp_PS_BASE |
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| 117 | SYMDEF sid_NEGATE, GL_NEGATE_BIT_ATI, ckp_PS_BASE |
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| 118 | SYMDEF sid_BX2, GL_2X_BIT_ATI | GL_BIAS_BIT_ATI, ckp_PS_BASE |
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| 119 | |
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| 120 | // seperator characters |
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| 121 | SYMDEF sid_COMMA, GL_NONE, ckp_PS_BASE |
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| 122 | SYMDEF sid_VALUE, GL_NONE, ckp_PS_BASE |
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| 123 | |
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| 124 | // PS_1_4 |
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| 125 | // temp R/W registers |
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| 126 | SYMDEF sid_R0, GL_REG_0_ATI, ckp_PS_1_4 |
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| 127 | SYMDEF sid_R1, GL_REG_1_ATI, ckp_PS_1_4 |
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| 128 | SYMDEF sid_R2, GL_REG_2_ATI, ckp_PS_1_4 |
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| 129 | SYMDEF sid_R3, GL_REG_3_ATI, ckp_PS_1_4 |
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| 130 | SYMDEF sid_R4, GL_REG_4_ATI, ckp_PS_1_4 |
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| 131 | SYMDEF sid_R5, GL_REG_5_ATI, ckp_PS_1_4 |
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| 132 | |
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| 133 | // textures |
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| 134 | SYMDEF sid_T0, GL_TEXTURE0_ARB, ckp_PS_1_4 |
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| 135 | SYMDEF sid_T1, GL_TEXTURE1_ARB, ckp_PS_1_4 |
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| 136 | SYMDEF sid_T2, GL_TEXTURE2_ARB, ckp_PS_1_4 |
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| 137 | SYMDEF sid_T3, GL_TEXTURE3_ARB, ckp_PS_1_4 |
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| 138 | SYMDEF sid_T4, GL_TEXTURE4_ARB, ckp_PS_1_4 |
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| 139 | SYMDEF sid_T5, GL_TEXTURE5_ARB, ckp_PS_1_4 |
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| 140 | SYMDEF sid_DP2ADD, GL_DOT2_ADD_ATI, ckp_PS_1_4 |
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| 141 | |
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| 142 | // modifiers |
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| 143 | SYMDEF sid_X8, GL_8X_BIT_ATI, ckp_PS_1_4 |
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| 144 | SYMDEF sid_D8, GL_EIGHTH_BIT_ATI, ckp_PS_1_4 |
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| 145 | SYMDEF sid_D4, GL_QUARTER_BIT_ATI, ckp_PS_1_4 |
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| 146 | |
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| 147 | // instructions |
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| 148 | SYMDEF sid_TEXCRD, GL_NONE, ckp_PS_1_4 |
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| 149 | SYMDEF sid_TEXLD, GL_NONE, ckp_PS_1_4 |
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| 150 | |
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| 151 | // texture swizzlers |
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| 152 | |
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| 153 | SYMDEF sid_STR, GL_SWIZZLE_STR_ATI - GL_SWIZZLE_STR_ATI, ckp_PS_1_4 |
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| 154 | SYMDEF sid_STQ, GL_SWIZZLE_STQ_ATI - GL_SWIZZLE_STR_ATI, ckp_PS_1_4 |
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| 155 | SYMDEF sid_STRDR, GL_SWIZZLE_STR_DR_ATI - GL_SWIZZLE_STR_ATI, ckp_PS_1_4 |
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| 156 | SYMDEF sid_STQDQ, GL_SWIZZLE_STQ_DQ_ATI - GL_SWIZZLE_STR_ATI, ckp_PS_1_4 |
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| 157 | |
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| 158 | SYMDEF sid_BEM, GL_NONE, ckp_PS_1_4 |
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| 159 | SYMDEF sid_PHASE, GL_NONE, ckp_PS_1_4 |
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| 160 | |
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| 161 | // PS_1_1 |
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| 162 | // temp R/W registers |
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| 163 | // r0, r1 are mapped to r4, r5 |
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| 164 | // t0 to t3 are mapped to r0 to r3 |
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| 165 | SYMDEF sid_1R0, GL_REG_4_ATI, ckp_PS_1_1 |
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| 166 | SYMDEF sid_1R1, GL_REG_5_ATI, ckp_PS_1_1 |
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| 167 | SYMDEF sid_1T0, GL_REG_0_ATI, ckp_PS_1_1 |
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| 168 | SYMDEF sid_1T1, GL_REG_1_ATI, ckp_PS_1_1 |
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| 169 | SYMDEF sid_1T2, GL_REG_2_ATI, ckp_PS_1_1 |
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| 170 | SYMDEF sid_1T3, GL_REG_3_ATI, ckp_PS_1_1 |
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| 171 | |
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| 172 | // instructions common to PS_1_1, PS_1_2, PS_1_3 |
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| 173 | SYMDEF sid_TEX, GL_NONE, ckp_PS_1_1 |
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| 174 | SYMDEF sid_TEXCOORD, GL_NONE, ckp_PS_1_1 |
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| 175 | SYMDEF sid_TEXM3X2PAD, GL_NONE, ckp_PS_1_1 |
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| 176 | SYMDEF sid_TEXM3X2TEX, GL_NONE, ckp_PS_1_1 |
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| 177 | SYMDEF sid_TEXM3X3PAD, GL_NONE, ckp_PS_1_1 |
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| 178 | SYMDEF sid_TEXM3X3TEX, GL_NONE, ckp_PS_1_1 |
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| 179 | SYMDEF sid_TEXM3X3SPEC, GL_NONE, ckp_PS_1_1 |
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| 180 | SYMDEF sid_TEXM3X3VSPEC, GL_NONE, ckp_PS_1_1 |
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| 181 | SYMDEF sid_TEXREG2AR, GL_NONE, ckp_PS_1_2 |
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| 182 | SYMDEF sid_TEXREG2GB, GL_NONE, ckp_PS_1_2 |
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| 183 | |
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| 184 | // PS_1_2 & PS_1_3 |
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| 185 | SYMDEF sid_TEXREG2RGB, GL_NONE, ckp_PS_1_2 |
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| 186 | SYMDEF sid_TEXDP3, GL_NONE, ckp_PS_1_2 |
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| 187 | SYMDEF sid_TEXDP3TEX, GL_NONE, ckp_PS_1_2 |
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| 188 | |
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| 189 | |
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| 190 | // Common |
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| 191 | SYMDEF sid_SKIP, GL_NONE, ckp_PS_BASE |
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| 192 | SYMDEF sid_PLUS, GL_NONE, ckp_PS_BASE |
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| 193 | |
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| 194 | // Non-Terminal Tokens |
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| 195 | SYMDEF sid_PROGRAM, GL_NONE, ckp_PS_BASE |
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| 196 | SYMDEF sid_PROGRAMTYPE, GL_NONE, ckp_PS_BASE |
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| 197 | SYMDEF sid_DECLCONSTS, GL_NONE, ckp_PS_BASE |
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| 198 | SYMDEF sid_DEFCONST, GL_NONE, ckp_PS_BASE |
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| 199 | SYMDEF sid_CONSTANT, GL_NONE, ckp_PS_BASE |
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| 200 | SYMDEF sid_COLOR, GL_NONE, ckp_PS_BASE |
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| 201 | SYMDEF sid_TEXSWIZZLE, GL_NONE, ckp_PS_BASE |
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| 202 | SYMDEF sid_UNARYOP, GL_NONE, ckp_PS_BASE |
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| 203 | SYMDEF sid_NUMVAL, GL_NONE, ckp_PS_BASE |
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| 204 | SYMDEF sid_SEPERATOR, GL_NONE, ckp_PS_BASE |
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| 205 | SYMDEF sid_ALUOPS, GL_NONE, ckp_PS_BASE |
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| 206 | SYMDEF sid_TEXMASK, GL_NONE, ckp_PS_BASE |
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| 207 | SYMDEF sid_TEXOP_PS1_1_3, GL_NONE, ckp_PS_1_1 |
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| 208 | SYMDEF sid_TEXOP_PS1_4, GL_NONE, ckp_PS_1_4 |
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| 209 | SYMDEF sid_ALU_STATEMENT, GL_NONE, ckp_PS_BASE |
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| 210 | SYMDEF sid_DSTMODSAT, GL_NONE, ckp_PS_BASE |
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| 211 | SYMDEF sid_UNARYOP_ARGS, GL_NONE, ckp_PS_BASE |
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| 212 | SYMDEF sid_REG_PS1_4, GL_NONE, ckp_PS_1_4 |
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| 213 | SYMDEF sid_TEX_PS1_4, GL_NONE, ckp_PS_1_4 |
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| 214 | SYMDEF sid_REG_PS1_1_3, GL_NONE, ckp_PS_1_1 |
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| 215 | SYMDEF sid_TEX_PS1_1_3, GL_NONE, ckp_PS_1_1 |
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| 216 | SYMDEF sid_DSTINFO, GL_NONE, ckp_PS_BASE |
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| 217 | SYMDEF sid_SRCINFO, GL_NONE, ckp_PS_BASE |
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| 218 | SYMDEF sid_BINARYOP_ARGS, GL_NONE, ckp_PS_BASE |
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| 219 | SYMDEF sid_TERNARYOP_ARGS, GL_NONE, ckp_PS_BASE |
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| 220 | SYMDEF sid_TEMPREG, GL_NONE, ckp_PS_BASE |
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| 221 | SYMDEF sid_DSTMASK, GL_NONE, ckp_PS_BASE |
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| 222 | SYMDEF sid_PRESRCMOD, GL_NONE, ckp_PS_BASE |
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| 223 | SYMDEF sid_SRCNAME, GL_NONE, ckp_PS_BASE |
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| 224 | SYMDEF sid_SRCREP, GL_NONE, ckp_PS_BASE |
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| 225 | SYMDEF sid_POSTSRCMOD, GL_NONE, ckp_PS_BASE |
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| 226 | SYMDEF sid_DSTMOD, GL_NONE, ckp_PS_BASE |
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| 227 | SYMDEF sid_DSTSAT, GL_NONE, ckp_PS_BASE |
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| 228 | SYMDEF sid_BINARYOP, GL_NONE, ckp_PS_BASE |
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| 229 | SYMDEF sid_TERNARYOP, GL_NONE, ckp_PS_BASE |
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| 230 | SYMDEF sid_TEXOPS_PHASE1, GL_NONE, ckp_PS_BASE |
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| 231 | SYMDEF sid_COISSUE, GL_NONE, ckp_PS_BASE |
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| 232 | SYMDEF sid_PHASEMARKER, GL_NONE, ckp_PS_1_4 |
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| 233 | SYMDEF sid_TEXOPS_PHASE2, GL_NONE, ckp_PS_1_4 |
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| 234 | SYMDEF sid_TEXREG_PS1_4, GL_NONE, ckp_PS_1_4 |
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| 235 | SYMDEF sid_TEXOPS_PS1_4, GL_NONE, ckp_PS_1_4 |
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| 236 | SYMDEF sid_TEXOPS_PS1_1_3, GL_NONE, ckp_PS_1_1 |
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| 237 | SYMDEF sid_TEXCISCOP_PS1_1_3, GL_NONE, ckp_PS_1_1 |
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| 238 | SYMEND |
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| 239 | }; |
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| 240 | |
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| 241 | |
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| 242 | // Rule Path Database for ps.1.x code based on extended Backus Naur Form notation |
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| 243 | |
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| 244 | // <> - non-terminal token |
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| 245 | #define _rule_ {otRULE, // ::= - rule definition |
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| 246 | #define _is_ ,0},{otAND, |
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| 247 | #define _and_ ,0},{otAND, // - blank space is an implied "AND" meaning the token is required |
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| 248 | #define _or_ ,0},{otOR, // | - or |
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| 249 | #define _optional_ ,0},{otOPTIONAL, // [] - optional |
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| 250 | #define _repeat_ ,0},{otREPEAT, // {} - repeat until fail |
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| 251 | #define _end_ ,0},{otEND,0,0,0}, |
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| 252 | #define _nt_ ,0 |
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| 253 | // " " - terminal token string |
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| 254 | |
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| 255 | PS_1_4::TokenRule PS_1_4::PS_1_x_RulePath[] = { |
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| 256 | |
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| 257 | _rule_ sid_PROGRAM, "Program" |
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| 258 | |
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| 259 | _is_ sid_PROGRAMTYPE _nt_ |
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| 260 | _optional_ sid_DECLCONSTS _nt_ |
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| 261 | _optional_ sid_TEXOPS_PHASE1 _nt_ |
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| 262 | _optional_ sid_ALUOPS _nt_ |
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| 263 | _optional_ sid_PHASEMARKER _nt_ |
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| 264 | _optional_ sid_TEXOPS_PHASE2 _nt_ |
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| 265 | _optional_ sid_ALUOPS _nt_ |
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| 266 | _end_ |
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| 267 | |
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| 268 | _rule_ sid_PROGRAMTYPE, "<ProgramType>" |
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| 269 | |
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| 270 | _is_ sid_PS_1_4, "ps.1.4" |
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| 271 | _or_ sid_PS_1_1, "ps.1.1" |
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| 272 | _or_ sid_PS_1_2, "ps.1.2" |
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| 273 | _or_ sid_PS_1_3, "ps.1.3" |
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| 274 | _end_ |
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| 275 | |
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| 276 | _rule_ sid_PHASEMARKER, "<PhaseMarker>" |
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| 277 | |
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| 278 | _is_ sid_PHASE, "phase" |
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| 279 | _end_ |
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| 280 | |
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| 281 | _rule_ sid_DECLCONSTS, "<DeclareConstants>" |
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| 282 | |
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| 283 | _repeat_ sid_DEFCONST _nt_ |
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| 284 | _end_ |
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| 285 | |
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| 286 | |
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| 287 | _rule_ sid_TEXOPS_PHASE1, "<TexOps_Phase1>" |
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| 288 | |
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| 289 | _is_ sid_TEXOPS_PS1_1_3 _nt_ |
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| 290 | _or_ sid_TEXOPS_PS1_4 _nt_ |
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| 291 | _end_ |
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| 292 | |
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| 293 | _rule_ sid_TEXOPS_PHASE2, "<TexOps_Phase2>" |
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| 294 | |
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| 295 | _is_ sid_TEXOPS_PS1_4 _nt_ |
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| 296 | _end_ |
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| 297 | |
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| 298 | _rule_ sid_NUMVAL, "<NumVal>" |
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| 299 | |
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| 300 | _is_ sid_VALUE, "Float Value" |
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| 301 | _end_ |
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| 302 | |
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| 303 | _rule_ sid_TEXOPS_PS1_1_3, "<TexOps_PS1_1_3>" |
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| 304 | |
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| 305 | _repeat_ sid_TEXOP_PS1_1_3 _nt_ |
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| 306 | _end_ |
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| 307 | |
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| 308 | _rule_ sid_TEXOPS_PS1_4, "<TexOps_PS1_4>" |
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| 309 | |
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| 310 | _repeat_ sid_TEXOP_PS1_4 _nt_ |
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| 311 | _end_ |
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| 312 | |
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| 313 | _rule_ sid_TEXOP_PS1_1_3, "<TexOp_PS1_1_3>" |
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| 314 | |
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| 315 | _is_ sid_TEXCISCOP_PS1_1_3 _nt_ |
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| 316 | _and_ sid_TEX_PS1_1_3 _nt_ |
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| 317 | _and_ sid_SEPERATOR _nt_ |
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| 318 | _and_ sid_TEX_PS1_1_3 _nt_ |
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| 319 | |
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| 320 | _or_ sid_TEXCOORD, "texcoord" |
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| 321 | _and_ sid_TEX_PS1_1_3 _nt_ |
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| 322 | |
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| 323 | _or_ sid_TEX, "tex" |
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| 324 | _and_ sid_TEX_PS1_1_3 _nt_ |
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| 325 | |
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| 326 | |
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| 327 | |
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| 328 | _end_ |
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| 329 | |
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| 330 | _rule_ sid_TEXOP_PS1_4, "<TexOp_PS1_4>" |
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| 331 | |
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| 332 | _is_ sid_TEXCRD, "texcrd" |
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| 333 | _and_ sid_REG_PS1_4 _nt_ |
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| 334 | _optional_ sid_TEXMASK _nt_ |
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| 335 | _and_ sid_SEPERATOR _nt_ |
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| 336 | _and_ sid_TEXREG_PS1_4 _nt_ |
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| 337 | |
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| 338 | _or_ sid_TEXLD, "texld" |
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| 339 | _and_ sid_REG_PS1_4 _nt_ |
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| 340 | _optional_ sid_TEXMASK _nt_ |
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| 341 | _and_ sid_SEPERATOR _nt_ |
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| 342 | _and_ sid_TEXREG_PS1_4 _nt_ |
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| 343 | _end_ |
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| 344 | |
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| 345 | _rule_ sid_ALUOPS, "<ALUOps>" |
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| 346 | |
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| 347 | _repeat_ sid_ALU_STATEMENT _nt_ |
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| 348 | _end_ |
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| 349 | |
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| 350 | _rule_ sid_ALU_STATEMENT, "<ALUStatement>" |
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| 351 | |
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| 352 | _is_ sid_COISSUE _nt_ |
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| 353 | _and_ sid_UNARYOP _nt_ |
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| 354 | _optional_ sid_DSTMODSAT _nt_ |
---|
| 355 | _and_ sid_UNARYOP_ARGS _nt_ |
---|
| 356 | |
---|
| 357 | _or_ sid_COISSUE _nt_ |
---|
| 358 | _and_ sid_BINARYOP _nt_ |
---|
| 359 | _optional_ sid_DSTMODSAT _nt_ |
---|
| 360 | _and_ sid_BINARYOP_ARGS _nt_ |
---|
| 361 | |
---|
| 362 | _or_ sid_COISSUE _nt_ |
---|
| 363 | _and_ sid_TERNARYOP _nt_ |
---|
| 364 | _optional_ sid_DSTMODSAT _nt_ |
---|
| 365 | _and_ sid_TERNARYOP_ARGS _nt_ |
---|
| 366 | _end_ |
---|
| 367 | |
---|
| 368 | |
---|
| 369 | _rule_ sid_TEXREG_PS1_4, "<TexReg_PS1_4>" |
---|
| 370 | |
---|
| 371 | _is_ sid_TEX_PS1_4 _nt_ |
---|
| 372 | _optional_ sid_TEXSWIZZLE _nt_ |
---|
| 373 | _or_ sid_REG_PS1_4 _nt_ |
---|
| 374 | _optional_ sid_TEXSWIZZLE _nt_ |
---|
| 375 | _end_ |
---|
| 376 | |
---|
| 377 | _rule_ sid_UNARYOP_ARGS, "<UnaryOpArgs>" |
---|
| 378 | |
---|
| 379 | _is_ sid_DSTINFO _nt_ |
---|
| 380 | _and_ sid_SRCINFO _nt_ |
---|
| 381 | _end_ |
---|
| 382 | |
---|
| 383 | _rule_ sid_BINARYOP_ARGS, "<BinaryOpArgs>" |
---|
| 384 | |
---|
| 385 | _is_ sid_DSTINFO _nt_ |
---|
| 386 | _and_ sid_SRCINFO _nt_ |
---|
| 387 | _and_ sid_SRCINFO _nt_ |
---|
| 388 | _end_ |
---|
| 389 | |
---|
| 390 | _rule_ sid_TERNARYOP_ARGS, "<TernaryOpArgs>" |
---|
| 391 | |
---|
| 392 | _is_ sid_DSTINFO _nt_ |
---|
| 393 | _and_ sid_SRCINFO _nt_ |
---|
| 394 | _and_ sid_SRCINFO _nt_ |
---|
| 395 | _and_ sid_SRCINFO _nt_ |
---|
| 396 | _end_ |
---|
| 397 | |
---|
| 398 | _rule_ sid_DSTINFO, "<DstInfo>" |
---|
| 399 | |
---|
| 400 | _is_ sid_TEMPREG _nt_ |
---|
| 401 | _optional_ sid_DSTMASK _nt_ |
---|
| 402 | _end_ |
---|
| 403 | |
---|
| 404 | _rule_ sid_SRCINFO, "<SrcInfo>" |
---|
| 405 | |
---|
| 406 | _is_ sid_SEPERATOR _nt_ |
---|
| 407 | _optional_ sid_PRESRCMOD _nt_ |
---|
| 408 | _and_ sid_SRCNAME _nt_ |
---|
| 409 | _optional_ sid_POSTSRCMOD _nt_ |
---|
| 410 | _optional_ sid_SRCREP _nt_ |
---|
| 411 | _end_ |
---|
| 412 | |
---|
| 413 | _rule_ sid_SRCNAME, "<SrcName>" |
---|
| 414 | |
---|
| 415 | _is_ sid_TEMPREG _nt_ |
---|
| 416 | _or_ sid_CONSTANT _nt_ |
---|
| 417 | _or_ sid_COLOR _nt_ |
---|
| 418 | _end_ |
---|
| 419 | |
---|
| 420 | _rule_ sid_DEFCONST, "<DefineConstant>" |
---|
| 421 | |
---|
| 422 | _is_ sid_DEF, "def" |
---|
| 423 | _and_ sid_CONSTANT _nt_ |
---|
| 424 | _and_ sid_SEPERATOR _nt_ |
---|
| 425 | _and_ sid_NUMVAL _nt_ |
---|
| 426 | _and_ sid_SEPERATOR _nt_ |
---|
| 427 | _and_ sid_NUMVAL _nt_ |
---|
| 428 | _and_ sid_SEPERATOR _nt_ |
---|
| 429 | _and_ sid_NUMVAL _nt_ |
---|
| 430 | _and_ sid_SEPERATOR _nt_ |
---|
| 431 | _and_ sid_NUMVAL _nt_ |
---|
| 432 | _end_ |
---|
| 433 | |
---|
| 434 | _rule_ sid_CONSTANT, "<Constant>" |
---|
| 435 | |
---|
| 436 | _is_ sid_C0, "c0" |
---|
| 437 | _or_ sid_C1, "c1" |
---|
| 438 | _or_ sid_C2, "c2" |
---|
| 439 | _or_ sid_C3, "c3" |
---|
| 440 | _or_ sid_C4, "c4" |
---|
| 441 | _or_ sid_C5, "c5" |
---|
| 442 | _or_ sid_C6, "c6" |
---|
| 443 | _or_ sid_C7, "c7" |
---|
| 444 | _end_ |
---|
| 445 | |
---|
| 446 | |
---|
| 447 | _rule_ sid_TEXCISCOP_PS1_1_3, "<TexCISCOp_PS1_1_3>" |
---|
| 448 | |
---|
| 449 | _is_ sid_TEXDP3TEX, "texdp3tex" |
---|
| 450 | _or_ sid_TEXDP3, "texdp3" |
---|
| 451 | _or_ sid_TEXM3X2PAD, "texm3x2pad" |
---|
| 452 | _or_ sid_TEXM3X2TEX, "texm3x2tex" |
---|
| 453 | _or_ sid_TEXM3X3PAD, "texm3x3pad" |
---|
| 454 | _or_ sid_TEXM3X3TEX, "texm3x3tex" |
---|
| 455 | _or_ sid_TEXM3X3SPEC, "texm3x3spec" |
---|
| 456 | _or_ sid_TEXM3X3VSPEC, "texm3x3vspec" |
---|
| 457 | _or_ sid_TEXREG2RGB, "texreg2rgb" |
---|
| 458 | _or_ sid_TEXREG2AR, "texreg2ar" |
---|
| 459 | _or_ sid_TEXREG2GB, "texreg2gb" |
---|
| 460 | _end_ |
---|
| 461 | |
---|
| 462 | |
---|
| 463 | _rule_ sid_TEXSWIZZLE, "<TexSwizzle>" |
---|
| 464 | |
---|
| 465 | _is_ sid_STQDQ, "_dw.xyw" |
---|
| 466 | _or_ sid_STQDQ, "_dw" |
---|
| 467 | _or_ sid_STQDQ, "_da.rga" |
---|
| 468 | _or_ sid_STQDQ, "_da" |
---|
| 469 | _or_ sid_STRDR, "_dz.xyz" |
---|
| 470 | _or_ sid_STRDR, "_dz" |
---|
| 471 | _or_ sid_STRDR, "_db.rgb" |
---|
| 472 | _or_ sid_STRDR, "_db" |
---|
| 473 | _or_ sid_STR, ".xyz" |
---|
| 474 | _or_ sid_STR, ".rgb" |
---|
| 475 | _or_ sid_STQ, ".xyw" |
---|
| 476 | _or_ sid_STQ, ".rga" |
---|
| 477 | _end_ |
---|
| 478 | |
---|
| 479 | _rule_ sid_TEXMASK, "<TexMask>" |
---|
| 480 | |
---|
| 481 | _is_ sid_RGB, ".rgb" |
---|
| 482 | _or_ sid_RGB, ".xyz" |
---|
| 483 | _or_ sid_RG, ".rg" |
---|
| 484 | _or_ sid_RG, ".xy" |
---|
| 485 | _end_ |
---|
| 486 | |
---|
| 487 | _rule_ sid_SEPERATOR, "<Seperator>" |
---|
| 488 | |
---|
| 489 | _is_ sid_COMMA, "," |
---|
| 490 | _end_ |
---|
| 491 | |
---|
| 492 | _rule_ sid_REG_PS1_4, "<Reg_PS1_4>" |
---|
| 493 | |
---|
| 494 | _is_ sid_R0, "r0" |
---|
| 495 | _or_ sid_R1, "r1" |
---|
| 496 | _or_ sid_R2, "r2" |
---|
| 497 | _or_ sid_R3, "r3" |
---|
| 498 | _or_ sid_R4, "r4" |
---|
| 499 | _or_ sid_R5, "r5" |
---|
| 500 | _end_ |
---|
| 501 | |
---|
| 502 | _rule_ sid_TEX_PS1_4, "<Tex_PS1_4>" |
---|
| 503 | |
---|
| 504 | _is_ sid_T0, "t0" |
---|
| 505 | _or_ sid_T1, "t1" |
---|
| 506 | _or_ sid_T2, "t2" |
---|
| 507 | _or_ sid_T3, "t3" |
---|
| 508 | _or_ sid_T4, "t4" |
---|
| 509 | _or_ sid_T5, "t5" |
---|
| 510 | _end_ |
---|
| 511 | |
---|
| 512 | _rule_ sid_REG_PS1_1_3, "<Reg_PS1_1_3>" |
---|
| 513 | |
---|
| 514 | _is_ sid_1R0, "r0" |
---|
| 515 | _or_ sid_1R1, "r1" |
---|
| 516 | _end_ |
---|
| 517 | |
---|
| 518 | _rule_ sid_TEX_PS1_1_3, "<Tex_PS1_1_3>" |
---|
| 519 | |
---|
| 520 | _is_ sid_1T0, "t0" |
---|
| 521 | _or_ sid_1T1, "t1" |
---|
| 522 | _or_ sid_1T2, "t2" |
---|
| 523 | _or_ sid_1T3, "t3" |
---|
| 524 | _end_ |
---|
| 525 | |
---|
| 526 | _rule_ sid_COLOR, "<Color>" |
---|
| 527 | |
---|
| 528 | _is_ sid_V0, "v0" |
---|
| 529 | _or_ sid_V1, "v1" |
---|
| 530 | _end_ |
---|
| 531 | |
---|
| 532 | |
---|
| 533 | _rule_ sid_TEMPREG, "<TempReg>" |
---|
| 534 | |
---|
| 535 | _is_ sid_REG_PS1_4 _nt_ |
---|
| 536 | _or_ sid_REG_PS1_1_3 _nt_ |
---|
| 537 | _or_ sid_TEX_PS1_1_3 _nt_ |
---|
| 538 | _end_ |
---|
| 539 | |
---|
| 540 | _rule_ sid_DSTMODSAT, "<DstModSat>" |
---|
| 541 | |
---|
| 542 | _optional_ sid_DSTMOD _nt_ |
---|
| 543 | _optional_ sid_DSTSAT _nt_ |
---|
| 544 | _end_ |
---|
| 545 | |
---|
| 546 | _rule_ sid_UNARYOP, "<UnaryOp>" |
---|
| 547 | |
---|
| 548 | _is_ sid_MOV, "mov" |
---|
| 549 | _end_ |
---|
| 550 | |
---|
| 551 | _rule_ sid_BINARYOP, "<BinaryOP>" |
---|
| 552 | |
---|
| 553 | _is_ sid_ADD, "add" |
---|
| 554 | _or_ sid_MUL, "mul" |
---|
| 555 | _or_ sid_SUB, "sub" |
---|
| 556 | _or_ sid_DP3, "dp3" |
---|
| 557 | _or_ sid_DP4, "dp4" |
---|
| 558 | _or_ sid_BEM, "bem" |
---|
| 559 | _end_ |
---|
| 560 | |
---|
| 561 | _rule_ sid_TERNARYOP, "<TernaryOp>" |
---|
| 562 | |
---|
| 563 | _is_ sid_MAD, "mad" |
---|
| 564 | _or_ sid_LRP, "lrp" |
---|
| 565 | _or_ sid_CND, "cnd" |
---|
| 566 | _or_ sid_CMP, "cmp" |
---|
| 567 | _end_ |
---|
| 568 | |
---|
| 569 | _rule_ sid_DSTMASK, "<DstMask>" |
---|
| 570 | |
---|
| 571 | _is_ sid_RGBA, ".rgba" |
---|
| 572 | _or_ sid_RGBA, ".xyzw" |
---|
| 573 | _or_ sid_RGB, ".rgb" |
---|
| 574 | _or_ sid_RGB, ".xyz" |
---|
| 575 | _or_ sid_RGA, ".xyw" |
---|
| 576 | _or_ sid_RGA, ".rga" |
---|
| 577 | _or_ sid_RBA, ".rba" |
---|
| 578 | _or_ sid_RBA, ".xzw" |
---|
| 579 | _or_ sid_GBA, ".gba" |
---|
| 580 | _or_ sid_GBA, ".yzw" |
---|
| 581 | _or_ sid_RG, ".rg" |
---|
| 582 | _or_ sid_RG, ".xy" |
---|
| 583 | _or_ sid_RB, ".xz" |
---|
| 584 | _or_ sid_RB, ".rb" |
---|
| 585 | _or_ sid_RA, ".xw" |
---|
| 586 | _or_ sid_RA, ".ra" |
---|
| 587 | _or_ sid_GB, ".gb" |
---|
| 588 | _or_ sid_GB, ".yz" |
---|
| 589 | _or_ sid_GA, ".yw" |
---|
| 590 | _or_ sid_GA, ".ga" |
---|
| 591 | _or_ sid_BA, ".zw" |
---|
| 592 | _or_ sid_BA, ".ba" |
---|
| 593 | _or_ sid_R, ".r" |
---|
| 594 | _or_ sid_R, ".x" |
---|
| 595 | _or_ sid_G, ".g" |
---|
| 596 | _or_ sid_G, ".y" |
---|
| 597 | _or_ sid_B, ".b" |
---|
| 598 | _or_ sid_B, ".z" |
---|
| 599 | _or_ sid_A, ".a" |
---|
| 600 | _or_ sid_A, ".w" |
---|
| 601 | _end_ |
---|
| 602 | |
---|
| 603 | _rule_ sid_SRCREP, "<SrcRep>" |
---|
| 604 | |
---|
| 605 | _is_ sid_RRRR, ".r" |
---|
| 606 | _or_ sid_RRRR, ".x" |
---|
| 607 | _or_ sid_GGGG, ".g" |
---|
| 608 | _or_ sid_GGGG, ".y" |
---|
| 609 | _or_ sid_BBBB, ".b" |
---|
| 610 | _or_ sid_BBBB, ".z" |
---|
| 611 | _or_ sid_AAAA, ".a" |
---|
| 612 | _or_ sid_AAAA, ".w" |
---|
| 613 | _end_ |
---|
| 614 | |
---|
| 615 | _rule_ sid_PRESRCMOD, "<PreSrcMod>" |
---|
| 616 | |
---|
| 617 | _is_ sid_INVERT, "1-" |
---|
| 618 | _or_ sid_INVERT, "1 -" |
---|
| 619 | _or_ sid_NEGATE, "-" |
---|
| 620 | _end_ |
---|
| 621 | |
---|
| 622 | _rule_ sid_POSTSRCMOD, "<PostSrcMod>" |
---|
| 623 | |
---|
| 624 | _is_ sid_BX2, "_bx2" |
---|
| 625 | _or_ sid_X2, "_x2" |
---|
| 626 | _or_ sid_BIAS, "_bias" |
---|
| 627 | _end_ |
---|
| 628 | |
---|
| 629 | _rule_ sid_DSTMOD, "<DstMod>" |
---|
| 630 | |
---|
| 631 | _is_ sid_X2, "_x2" |
---|
| 632 | _or_ sid_X4, "_x4" |
---|
| 633 | _or_ sid_D2, "_d2" |
---|
| 634 | _or_ sid_X8, "_x8" |
---|
| 635 | _or_ sid_D4, "_d4" |
---|
| 636 | _or_ sid_D8, "_d8" |
---|
| 637 | _end_ |
---|
| 638 | |
---|
| 639 | _rule_ sid_DSTSAT, "<DstSat>" |
---|
| 640 | |
---|
| 641 | _is_ sid_SAT, "_sat" |
---|
| 642 | _end_ |
---|
| 643 | |
---|
| 644 | _rule_ sid_COISSUE, "<CoIssue>" |
---|
| 645 | |
---|
| 646 | _optional_ sid_PLUS, "+" |
---|
| 647 | _end_ |
---|
| 648 | |
---|
| 649 | }; |
---|
| 650 | |
---|
| 651 | //***************************** MACROs for PS1_1 , PS1_2, PS1_3 CISC instructions ************************************** |
---|
| 652 | |
---|
| 653 | // macro to make the macro text data easier to read |
---|
| 654 | #define _token_ ,0,0},{ |
---|
| 655 | #define _token_end_ ,0,0} |
---|
| 656 | // macro token expansion for ps_1_2 instruction: texreg2ar |
---|
| 657 | PS_1_4::TokenInst PS_1_4::texreg2ar[] = { |
---|
| 658 | // mov r(x).r, r(y).a |
---|
| 659 | { sid_UNARYOP, sid_MOV |
---|
| 660 | _token_ sid_REG_PS1_4, sid_R1 |
---|
| 661 | _token_ sid_DSTMASK, sid_R |
---|
| 662 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 663 | _token_ sid_REG_PS1_4, sid_R0 |
---|
| 664 | _token_ sid_SRCREP, sid_AAAA |
---|
| 665 | |
---|
| 666 | // mov r(x).g, r(y).r |
---|
| 667 | _token_ sid_UNARYOP, sid_MOV |
---|
| 668 | _token_ sid_REG_PS1_4, sid_R1 |
---|
| 669 | _token_ sid_DSTMASK, sid_G |
---|
| 670 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 671 | _token_ sid_REG_PS1_4, sid_R0 |
---|
| 672 | _token_ sid_SRCREP, sid_RRRR |
---|
| 673 | |
---|
| 674 | // texld r(x), r(x) |
---|
| 675 | _token_ sid_TEXOP_PS1_4, sid_TEXLD |
---|
| 676 | _token_ sid_REG_PS1_4, sid_R1 |
---|
| 677 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 678 | _token_ sid_REG_PS1_4, sid_R1 |
---|
| 679 | _token_end_ |
---|
| 680 | }; |
---|
| 681 | |
---|
| 682 | PS_1_4::RegModOffset PS_1_4::texreg2xx_RegMods[] = { |
---|
| 683 | {1, R_BASE, 0}, |
---|
| 684 | {7, R_BASE, 0}, |
---|
| 685 | {13, R_BASE, 0}, |
---|
| 686 | {15, R_BASE, 0}, |
---|
| 687 | {4, R_BASE, 1}, |
---|
| 688 | {10, R_BASE, 1}, |
---|
| 689 | |
---|
| 690 | }; |
---|
| 691 | |
---|
| 692 | PS_1_4::MacroRegModify PS_1_4::texreg2ar_MacroMods = { |
---|
| 693 | texreg2ar, ARRAYSIZE(texreg2ar), |
---|
| 694 | texreg2xx_RegMods, ARRAYSIZE(texreg2xx_RegMods) |
---|
| 695 | }; |
---|
| 696 | |
---|
| 697 | // macro token expansion for ps_1_2 instruction: texreg2gb |
---|
| 698 | PS_1_4::TokenInst PS_1_4::texreg2gb[] = { |
---|
| 699 | // mov r(x).r, r(y).g |
---|
| 700 | { sid_UNARYOP, sid_MOV |
---|
| 701 | _token_ sid_REG_PS1_4, sid_R1 |
---|
| 702 | _token_ sid_DSTMASK, sid_R |
---|
| 703 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 704 | _token_ sid_REG_PS1_4, sid_R0 |
---|
| 705 | _token_ sid_SRCREP, sid_GGGG |
---|
| 706 | |
---|
| 707 | // mov r(x).g, r(y).b |
---|
| 708 | _token_ sid_UNARYOP, sid_MOV |
---|
| 709 | _token_ sid_REG_PS1_4, sid_R1 |
---|
| 710 | _token_ sid_DSTMASK, sid_G |
---|
| 711 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 712 | _token_ sid_REG_PS1_4, sid_R0 |
---|
| 713 | _token_ sid_SRCREP, sid_BBBB |
---|
| 714 | |
---|
| 715 | // texld r(x), r(x) |
---|
| 716 | _token_ sid_TEXOP_PS1_4, sid_TEXLD |
---|
| 717 | _token_ sid_REG_PS1_4, sid_R1 |
---|
| 718 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 719 | _token_ sid_REG_PS1_4, sid_R1 |
---|
| 720 | _token_end_ |
---|
| 721 | }; |
---|
| 722 | |
---|
| 723 | PS_1_4::MacroRegModify PS_1_4::texreg2gb_MacroMods = { |
---|
| 724 | texreg2gb, ARRAYSIZE(texreg2gb), |
---|
| 725 | texreg2xx_RegMods, ARRAYSIZE(texreg2xx_RegMods) |
---|
| 726 | }; |
---|
| 727 | |
---|
| 728 | |
---|
| 729 | // macro token expansion for ps_1_1 instruction: texdp3 |
---|
| 730 | PS_1_4::TokenInst PS_1_4::texdp3[] = { |
---|
| 731 | // texcoord t(x) |
---|
| 732 | { sid_TEXOP_PS1_1_3, sid_TEXCOORD |
---|
| 733 | _token_ sid_TEX_PS1_1_3, sid_1T1 |
---|
| 734 | |
---|
| 735 | // dp3 r(x), r(x), r(y) |
---|
| 736 | _token_ sid_BINARYOP, sid_DP3 |
---|
| 737 | _token_ sid_REG_PS1_4, sid_R1 |
---|
| 738 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 739 | _token_ sid_REG_PS1_4, sid_R1 |
---|
| 740 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 741 | _token_ sid_REG_PS1_4, sid_R0 |
---|
| 742 | _token_end_ |
---|
| 743 | }; |
---|
| 744 | |
---|
| 745 | |
---|
| 746 | PS_1_4::RegModOffset PS_1_4::texdp3_RegMods[] = { |
---|
| 747 | {1, T_BASE, 0}, |
---|
| 748 | {3, R_BASE, 0}, |
---|
| 749 | {5, R_BASE, 0}, |
---|
| 750 | {7, R_BASE, 1}, |
---|
| 751 | |
---|
| 752 | }; |
---|
| 753 | |
---|
| 754 | |
---|
| 755 | PS_1_4::MacroRegModify PS_1_4::texdp3_MacroMods = { |
---|
| 756 | texdp3, ARRAYSIZE(texdp3), |
---|
| 757 | texdp3_RegMods, ARRAYSIZE(texdp3_RegMods) |
---|
| 758 | }; |
---|
| 759 | |
---|
| 760 | |
---|
| 761 | // macro token expansion for ps_1_1 instruction: texdp3tex |
---|
| 762 | PS_1_4::TokenInst PS_1_4::texdp3tex[] = { |
---|
| 763 | // texcoord t(x) |
---|
| 764 | { sid_TEXOP_PS1_1_3, sid_TEXCOORD |
---|
| 765 | _token_ sid_TEX_PS1_1_3, sid_1T1 |
---|
| 766 | |
---|
| 767 | // dp3 r1, r(x), r(y) |
---|
| 768 | _token_ sid_BINARYOP, sid_DP3 |
---|
| 769 | _token_ sid_REG_PS1_4, sid_R1 |
---|
| 770 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 771 | _token_ sid_REG_PS1_4, sid_R1 |
---|
| 772 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 773 | _token_ sid_REG_PS1_4, sid_R0 |
---|
| 774 | |
---|
| 775 | // texld r(x), r(x) |
---|
| 776 | _token_ sid_TEXOP_PS1_4, sid_TEXLD |
---|
| 777 | _token_ sid_REG_PS1_4, sid_R1 |
---|
| 778 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 779 | _token_ sid_REG_PS1_4, sid_R1 |
---|
| 780 | _token_end_ |
---|
| 781 | }; |
---|
| 782 | |
---|
| 783 | |
---|
| 784 | PS_1_4::RegModOffset PS_1_4::texdp3tex_RegMods[] = { |
---|
| 785 | {1, T_BASE, 0}, |
---|
| 786 | {3, R_BASE, 0}, |
---|
| 787 | {5, R_BASE, 0}, |
---|
| 788 | {7, R_BASE, 1}, |
---|
| 789 | {9, R_BASE, 1}, |
---|
| 790 | {11, R_BASE, 1}, |
---|
| 791 | |
---|
| 792 | }; |
---|
| 793 | |
---|
| 794 | |
---|
| 795 | PS_1_4::MacroRegModify PS_1_4::texdp3tex_MacroMods = { |
---|
| 796 | texdp3tex, ARRAYSIZE(texdp3tex), |
---|
| 797 | texdp3tex_RegMods, ARRAYSIZE(texdp3tex_RegMods) |
---|
| 798 | }; |
---|
| 799 | |
---|
| 800 | |
---|
| 801 | // macro token expansion for ps_1_1 instruction: texm3x2pad |
---|
| 802 | PS_1_4::TokenInst PS_1_4::texm3x2pad[] = { |
---|
| 803 | // texcoord t(x) |
---|
| 804 | { sid_TEXOP_PS1_1_3, sid_TEXCOORD |
---|
| 805 | _token_ sid_TEX_PS1_1_3, sid_1T0 |
---|
| 806 | |
---|
| 807 | // dp3 r4.r, r(x), r(y) |
---|
| 808 | _token_ sid_BINARYOP, sid_DP3 |
---|
| 809 | _token_ sid_REG_PS1_4, sid_R4 |
---|
| 810 | _token_ sid_DSTMASK, sid_R |
---|
| 811 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 812 | _token_ sid_REG_PS1_4, sid_R1 |
---|
| 813 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 814 | _token_ sid_REG_PS1_4, sid_R0 |
---|
| 815 | _token_end_ |
---|
| 816 | |
---|
| 817 | }; |
---|
| 818 | |
---|
| 819 | |
---|
| 820 | PS_1_4::RegModOffset PS_1_4::texm3xxpad_RegMods[] = { |
---|
| 821 | {1, T_BASE, 0}, |
---|
| 822 | {6, R_BASE, 0}, |
---|
| 823 | {8, R_BASE, 1}, |
---|
| 824 | }; |
---|
| 825 | |
---|
| 826 | |
---|
| 827 | PS_1_4::MacroRegModify PS_1_4::texm3x2pad_MacroMods = { |
---|
| 828 | texm3x2pad, ARRAYSIZE(texm3x2pad), |
---|
| 829 | texm3xxpad_RegMods, ARRAYSIZE(texm3xxpad_RegMods) |
---|
| 830 | }; |
---|
| 831 | |
---|
| 832 | |
---|
| 833 | // macro token expansion for ps_1_1 instruction: texm3x2tex |
---|
| 834 | PS_1_4::TokenInst PS_1_4::texm3x2tex[] = { |
---|
| 835 | // texcoord t(x) |
---|
| 836 | { sid_TEXOP_PS1_1_3, sid_TEXCOORD |
---|
| 837 | _token_ sid_TEX_PS1_1_3, sid_1T1 |
---|
| 838 | |
---|
| 839 | // dp3 r4.g, r(x), r(y) |
---|
| 840 | _token_ sid_BINARYOP, sid_DP3 |
---|
| 841 | _token_ sid_REG_PS1_4, sid_R4 |
---|
| 842 | _token_ sid_DSTMASK, sid_G |
---|
| 843 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 844 | _token_ sid_REG_PS1_4, sid_R1 |
---|
| 845 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 846 | _token_ sid_REG_PS1_4, sid_R0 |
---|
| 847 | |
---|
| 848 | // texld r(x), r4 |
---|
| 849 | _token_ sid_TEXOP_PS1_4, sid_TEXLD |
---|
| 850 | _token_ sid_REG_PS1_4, sid_R1 |
---|
| 851 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 852 | _token_ sid_REG_PS1_4, sid_R4 |
---|
| 853 | _token_end_ |
---|
| 854 | |
---|
| 855 | }; |
---|
| 856 | |
---|
| 857 | PS_1_4::RegModOffset PS_1_4::texm3xxtex_RegMods[] = { |
---|
| 858 | {1, T_BASE, 0}, |
---|
| 859 | {6, R_BASE, 0}, |
---|
| 860 | {8, R_BASE, 1}, |
---|
| 861 | {10, R_BASE, 0} |
---|
| 862 | }; |
---|
| 863 | |
---|
| 864 | PS_1_4::MacroRegModify PS_1_4::texm3x2tex_MacroMods = { |
---|
| 865 | texm3x2tex, ARRAYSIZE(texm3x2tex), |
---|
| 866 | texm3xxtex_RegMods, ARRAYSIZE(texm3xxtex_RegMods) |
---|
| 867 | }; |
---|
| 868 | |
---|
| 869 | // macro token expansion for ps_1_1 instruction: texm3x3tex |
---|
| 870 | PS_1_4::TokenInst PS_1_4::texm3x3pad[] = { |
---|
| 871 | // texcoord t(x) |
---|
| 872 | { sid_TEXOP_PS1_1_3, sid_TEXCOORD |
---|
| 873 | _token_ sid_TEX_PS1_1_3, sid_1T0 |
---|
| 874 | |
---|
| 875 | // dp3 r4.b, r(x), r(y) |
---|
| 876 | _token_ sid_BINARYOP, sid_DP3 |
---|
| 877 | _token_ sid_REG_PS1_4, sid_R4 |
---|
| 878 | _token_ sid_DSTMASK, sid_B |
---|
| 879 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 880 | _token_ sid_REG_PS1_4, sid_R1 |
---|
| 881 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 882 | _token_ sid_REG_PS1_4, sid_R0 |
---|
| 883 | _token_end_ |
---|
| 884 | |
---|
| 885 | }; |
---|
| 886 | |
---|
| 887 | |
---|
| 888 | PS_1_4::MacroRegModify PS_1_4::texm3x3pad_MacroMods = { |
---|
| 889 | texm3x3pad, ARRAYSIZE(texm3x3pad), |
---|
| 890 | texm3xxpad_RegMods, ARRAYSIZE(texm3xxpad_RegMods) |
---|
| 891 | }; |
---|
| 892 | |
---|
| 893 | |
---|
| 894 | // macro token expansion for ps_1_1 instruction: texm3x3pad |
---|
| 895 | PS_1_4::TokenInst PS_1_4::texm3x3tex[] = { |
---|
| 896 | // texcoord t(x) |
---|
| 897 | { sid_TEXOP_PS1_1_3, sid_TEXCOORD |
---|
| 898 | _token_ sid_TEX_PS1_1_3, sid_1T1 |
---|
| 899 | |
---|
| 900 | // dp3 r4.b, r(x), r(y) |
---|
| 901 | _token_ sid_BINARYOP, sid_DP3 |
---|
| 902 | _token_ sid_REG_PS1_4, sid_R4 |
---|
| 903 | _token_ sid_DSTMASK, sid_B |
---|
| 904 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 905 | _token_ sid_REG_PS1_4, sid_R1 |
---|
| 906 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 907 | _token_ sid_REG_PS1_4, sid_R0 |
---|
| 908 | |
---|
| 909 | // texld r1, r4 |
---|
| 910 | _token_ sid_TEXOP_PS1_4, sid_TEXLD |
---|
| 911 | _token_ sid_REG_PS1_4, sid_R1 |
---|
| 912 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 913 | _token_ sid_REG_PS1_4, sid_R4 |
---|
| 914 | _token_end_ |
---|
| 915 | }; |
---|
| 916 | |
---|
| 917 | |
---|
| 918 | |
---|
| 919 | |
---|
| 920 | |
---|
| 921 | |
---|
| 922 | PS_1_4::MacroRegModify PS_1_4::texm3x3tex_MacroMods = { |
---|
| 923 | texm3x3tex, ARRAYSIZE(texm3x3tex), |
---|
| 924 | texm3xxtex_RegMods, ARRAYSIZE(texm3xxtex_RegMods) |
---|
| 925 | }; |
---|
| 926 | |
---|
| 927 | |
---|
| 928 | // macro token expansion for ps_1_1 instruction: texm3x3spec |
---|
| 929 | PS_1_4::TokenInst PS_1_4::texm3x3spec[] = { |
---|
| 930 | // texcoord t(x) |
---|
| 931 | { sid_TEXOP_PS1_1_3, sid_TEXCOORD |
---|
| 932 | _token_ sid_TEX_PS1_1_3, sid_1T3 |
---|
| 933 | |
---|
| 934 | // dp3 r4.b, r3, r(x) |
---|
| 935 | _token_ sid_BINARYOP, sid_DP3 |
---|
| 936 | _token_ sid_REG_PS1_4, sid_R4 |
---|
| 937 | _token_ sid_DSTMASK, sid_B |
---|
| 938 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 939 | _token_ sid_REG_PS1_4, sid_R3 |
---|
| 940 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 941 | _token_ sid_REG_PS1_4, sid_R0 |
---|
| 942 | |
---|
| 943 | // dp3_x2 r3, r4, c(x) |
---|
| 944 | _token_ sid_BINARYOP, sid_DP3 |
---|
| 945 | _token_ sid_DSTMOD, sid_X2 |
---|
| 946 | _token_ sid_REG_PS1_4, sid_R3 |
---|
| 947 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 948 | _token_ sid_REG_PS1_4, sid_R4 |
---|
| 949 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 950 | _token_ sid_CONSTANT, sid_C0 |
---|
| 951 | |
---|
| 952 | // mul r3, r3, c(x) |
---|
| 953 | _token_ sid_UNARYOP, sid_MUL |
---|
| 954 | _token_ sid_REG_PS1_4, sid_R3 |
---|
| 955 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 956 | _token_ sid_REG_PS1_4, sid_R3 |
---|
| 957 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 958 | _token_ sid_CONSTANT, sid_C0 |
---|
| 959 | |
---|
| 960 | // dp3 r2, r4, r4 |
---|
| 961 | _token_ sid_BINARYOP, sid_DP3 |
---|
| 962 | _token_ sid_REG_PS1_4, sid_R2 |
---|
| 963 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 964 | _token_ sid_REG_PS1_4, sid_R4 |
---|
| 965 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 966 | _token_ sid_REG_PS1_4, sid_R4 |
---|
| 967 | |
---|
| 968 | // mad r4.rgb, 1-c(x), r2, r3 |
---|
| 969 | _token_ sid_TERNARYOP, sid_MAD |
---|
| 970 | _token_ sid_REG_PS1_4, sid_R4 |
---|
| 971 | _token_ sid_DSTMASK, sid_RGB |
---|
| 972 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 973 | _token_ sid_PRESRCMOD, sid_INVERT |
---|
| 974 | _token_ sid_CONSTANT, sid_C0 |
---|
| 975 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 976 | _token_ sid_REG_PS1_4, sid_R2 |
---|
| 977 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 978 | _token_ sid_REG_PS1_4, sid_R3 |
---|
| 979 | |
---|
| 980 | // + mov r4.a, r2.r |
---|
| 981 | _token_ sid_UNARYOP, sid_MOV |
---|
| 982 | _token_ sid_REG_PS1_4, sid_R4 |
---|
| 983 | _token_ sid_DSTMASK, sid_A |
---|
| 984 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 985 | _token_ sid_REG_PS1_4, sid_R2 |
---|
| 986 | _token_ sid_SRCREP, sid_RRRR |
---|
| 987 | |
---|
| 988 | // texld r3, r4.xyz_dz |
---|
| 989 | _token_ sid_TEXOP_PS1_4, sid_TEXLD |
---|
| 990 | _token_ sid_REG_PS1_4, sid_R3 |
---|
| 991 | _token_ sid_SEPERATOR, sid_COMMA |
---|
| 992 | _token_ sid_REG_PS1_4, sid_R4 |
---|
| 993 | _token_ sid_TEXSWIZZLE, sid_STRDR |
---|
| 994 | _token_end_ |
---|
| 995 | |
---|
| 996 | }; |
---|
| 997 | |
---|
| 998 | PS_1_4::RegModOffset PS_1_4::texm3x3spec_RegMods[] = { |
---|
| 999 | {8, R_BASE, 1}, |
---|
| 1000 | {15, R_BASE, 2}, |
---|
| 1001 | {21, C_BASE, 2}, |
---|
| 1002 | {33, C_BASE, 2}, |
---|
| 1003 | |
---|
| 1004 | }; |
---|
| 1005 | |
---|
| 1006 | PS_1_4::MacroRegModify PS_1_4::texm3x3spec_MacroMods = { |
---|
| 1007 | texm3x3spec, ARRAYSIZE(texm3x3spec), |
---|
| 1008 | texm3x3spec_RegMods, ARRAYSIZE(texm3x3spec_RegMods) |
---|
| 1009 | }; |
---|
| 1010 | |
---|
| 1011 | |
---|
| 1012 | /* ********************* END OF CLASS STATIC DATA ********************************* */ |
---|
| 1013 | |
---|
| 1014 | PS_1_4::PS_1_4() |
---|
| 1015 | { |
---|
| 1016 | // allocate enough room for a large pixel shader |
---|
| 1017 | mPhase1TEX_mi.reserve(50); |
---|
| 1018 | mPhase2TEX_mi.reserve(30); |
---|
| 1019 | mPhase1ALU_mi.reserve(100); |
---|
| 1020 | mPhase2ALU_mi.reserve(100); |
---|
| 1021 | |
---|
| 1022 | |
---|
| 1023 | mSymbolTypeLib = PS_1_4_SymbolTypeLib; |
---|
| 1024 | mSymbolTypeLibCnt = ARRAYSIZE(PS_1_4_SymbolTypeLib); |
---|
| 1025 | mRootRulePath = PS_1_x_RulePath; |
---|
| 1026 | mRulePathLibCnt = ARRAYSIZE(PS_1_x_RulePath); |
---|
| 1027 | // tell compiler what the symbol id is for a numeric value |
---|
| 1028 | mValueID = sid_VALUE; |
---|
| 1029 | // The type library must have text definitions initialized |
---|
| 1030 | // before compiler is invoked |
---|
| 1031 | |
---|
| 1032 | // only need to initialize the rule database once |
---|
| 1033 | if(LibInitialized == false) { |
---|
| 1034 | InitSymbolTypeLib(); |
---|
| 1035 | LibInitialized = true; |
---|
| 1036 | } |
---|
| 1037 | |
---|
| 1038 | // set initial context to recognize PS base instructions |
---|
| 1039 | mActiveContexts = ckp_PS_BASE; |
---|
| 1040 | |
---|
| 1041 | } |
---|
| 1042 | |
---|
| 1043 | |
---|
| 1044 | bool PS_1_4::bindMachineInstInPassToFragmentShader(const MachineInstContainer & PassMachineInstructions) |
---|
| 1045 | { |
---|
| 1046 | size_t instIDX = 0; |
---|
| 1047 | size_t instCount = PassMachineInstructions.size(); |
---|
| 1048 | bool error = false; |
---|
| 1049 | |
---|
| 1050 | while ((instIDX < instCount) && !error) { |
---|
| 1051 | switch(PassMachineInstructions[instIDX]) { |
---|
| 1052 | case mi_COLOROP1: |
---|
| 1053 | if((instIDX+7) < instCount) |
---|
| 1054 | glColorFragmentOp1ATI(PassMachineInstructions[instIDX+1], // op |
---|
| 1055 | PassMachineInstructions[instIDX+2], // dst |
---|
| 1056 | PassMachineInstructions[instIDX+3], // dstMask |
---|
| 1057 | PassMachineInstructions[instIDX+4], // dstMod |
---|
| 1058 | PassMachineInstructions[instIDX+5], // arg1 |
---|
| 1059 | PassMachineInstructions[instIDX+6], // arg1Rep |
---|
| 1060 | PassMachineInstructions[instIDX+7]);// arg1Mod |
---|
| 1061 | instIDX += 8; |
---|
| 1062 | break; |
---|
| 1063 | |
---|
| 1064 | case mi_COLOROP2: |
---|
| 1065 | if((instIDX+10) < instCount) |
---|
| 1066 | glColorFragmentOp2ATI(PassMachineInstructions[instIDX+1], // op |
---|
| 1067 | PassMachineInstructions[instIDX+2], // dst |
---|
| 1068 | PassMachineInstructions[instIDX+3], // dstMask |
---|
| 1069 | PassMachineInstructions[instIDX+4], // dstMod |
---|
| 1070 | PassMachineInstructions[instIDX+5], // arg1 |
---|
| 1071 | PassMachineInstructions[instIDX+6], // arg1Rep |
---|
| 1072 | PassMachineInstructions[instIDX+7], // arg1Mod |
---|
| 1073 | PassMachineInstructions[instIDX+8], // arg2 |
---|
| 1074 | PassMachineInstructions[instIDX+9], // arg2Rep |
---|
| 1075 | PassMachineInstructions[instIDX+10]);// arg2Mod |
---|
| 1076 | instIDX += 11; |
---|
| 1077 | break; |
---|
| 1078 | |
---|
| 1079 | case mi_COLOROP3: |
---|
| 1080 | if((instIDX+13) < instCount) |
---|
| 1081 | glColorFragmentOp3ATI(PassMachineInstructions[instIDX+1], // op |
---|
| 1082 | PassMachineInstructions[instIDX+2], // dst |
---|
| 1083 | PassMachineInstructions[instIDX+3], // dstMask |
---|
| 1084 | PassMachineInstructions[instIDX+4], // dstMod |
---|
| 1085 | PassMachineInstructions[instIDX+5], // arg1 |
---|
| 1086 | PassMachineInstructions[instIDX+6], // arg1Rep |
---|
| 1087 | PassMachineInstructions[instIDX+7], // arg1Mod |
---|
| 1088 | PassMachineInstructions[instIDX+8], // arg2 |
---|
| 1089 | PassMachineInstructions[instIDX+9], // arg2Rep |
---|
| 1090 | PassMachineInstructions[instIDX+10], // arg2Mod |
---|
| 1091 | PassMachineInstructions[instIDX+11], // arg2 |
---|
| 1092 | PassMachineInstructions[instIDX+12], // arg2Rep |
---|
| 1093 | PassMachineInstructions[instIDX+13]);// arg2Mod |
---|
| 1094 | instIDX += 14; |
---|
| 1095 | break; |
---|
| 1096 | |
---|
| 1097 | case mi_ALPHAOP1: |
---|
| 1098 | if((instIDX+6) < instCount) |
---|
| 1099 | glAlphaFragmentOp1ATI(PassMachineInstructions[instIDX+1], // op |
---|
| 1100 | PassMachineInstructions[instIDX+2], // dst |
---|
| 1101 | PassMachineInstructions[instIDX+3], // dstMod |
---|
| 1102 | PassMachineInstructions[instIDX+4], // arg1 |
---|
| 1103 | PassMachineInstructions[instIDX+5], // arg1Rep |
---|
| 1104 | PassMachineInstructions[instIDX+6]); // arg1Mod |
---|
| 1105 | instIDX += 7; |
---|
| 1106 | break; |
---|
| 1107 | |
---|
| 1108 | case mi_ALPHAOP2: |
---|
| 1109 | if((instIDX+9) < instCount) |
---|
| 1110 | glAlphaFragmentOp2ATI(PassMachineInstructions[instIDX+1], // op |
---|
| 1111 | PassMachineInstructions[instIDX+2], // dst |
---|
| 1112 | PassMachineInstructions[instIDX+3], // dstMod |
---|
| 1113 | PassMachineInstructions[instIDX+4], // arg1 |
---|
| 1114 | PassMachineInstructions[instIDX+5], // arg1Rep |
---|
| 1115 | PassMachineInstructions[instIDX+6], // arg1Mod |
---|
| 1116 | PassMachineInstructions[instIDX+7], // arg2 |
---|
| 1117 | PassMachineInstructions[instIDX+8], // arg2Rep |
---|
| 1118 | PassMachineInstructions[instIDX+9]); // arg2Mod |
---|
| 1119 | instIDX += 10; |
---|
| 1120 | break; |
---|
| 1121 | |
---|
| 1122 | case mi_ALPHAOP3: |
---|
| 1123 | if((instIDX+12) < instCount) |
---|
| 1124 | glAlphaFragmentOp3ATI(PassMachineInstructions[instIDX+1], // op |
---|
| 1125 | PassMachineInstructions[instIDX+2], // dst |
---|
| 1126 | PassMachineInstructions[instIDX+3], // dstMod |
---|
| 1127 | PassMachineInstructions[instIDX+4], // arg1 |
---|
| 1128 | PassMachineInstructions[instIDX+5], // arg1Rep |
---|
| 1129 | PassMachineInstructions[instIDX+6], // arg1Mod |
---|
| 1130 | PassMachineInstructions[instIDX+7], // arg2 |
---|
| 1131 | PassMachineInstructions[instIDX+8], // arg2Rep |
---|
| 1132 | PassMachineInstructions[instIDX+9], // arg2Mod |
---|
| 1133 | PassMachineInstructions[instIDX+10], // arg2 |
---|
| 1134 | PassMachineInstructions[instIDX+11], // arg2Rep |
---|
| 1135 | PassMachineInstructions[instIDX+12]); // arg2Mod |
---|
| 1136 | instIDX += 13; |
---|
| 1137 | break; |
---|
| 1138 | |
---|
| 1139 | case mi_SETCONSTANTS: |
---|
| 1140 | if((instIDX+2) < instCount) |
---|
| 1141 | glSetFragmentShaderConstantATI(PassMachineInstructions[instIDX+1], // dst |
---|
| 1142 | &mConstants[PassMachineInstructions[instIDX+2]]); |
---|
| 1143 | instIDX += 3; |
---|
| 1144 | break; |
---|
| 1145 | |
---|
| 1146 | case mi_PASSTEXCOORD: |
---|
| 1147 | if((instIDX+3) < instCount) |
---|
| 1148 | glPassTexCoordATI(PassMachineInstructions[instIDX+1], // dst |
---|
| 1149 | PassMachineInstructions[instIDX+2], // coord |
---|
| 1150 | PassMachineInstructions[instIDX+3]); // swizzle |
---|
| 1151 | instIDX += 4; |
---|
| 1152 | break; |
---|
| 1153 | |
---|
| 1154 | case mi_SAMPLEMAP: |
---|
| 1155 | if((instIDX+3) < instCount) |
---|
| 1156 | glSampleMapATI(PassMachineInstructions[instIDX+1], // dst |
---|
| 1157 | PassMachineInstructions[instIDX+2], // interp |
---|
| 1158 | PassMachineInstructions[instIDX+3]); // swizzle |
---|
| 1159 | instIDX += 4; |
---|
| 1160 | break; |
---|
| 1161 | |
---|
| 1162 | default: |
---|
| 1163 | instIDX = instCount; |
---|
| 1164 | // should generate an error since an unknown instruction was found |
---|
| 1165 | // instead for now the bind process is terminated and the fragment program may still function |
---|
| 1166 | // but its output may not be what was programmed |
---|
| 1167 | |
---|
| 1168 | } // end of switch |
---|
| 1169 | |
---|
| 1170 | error = (glGetError() != GL_NO_ERROR); |
---|
| 1171 | }// end of while |
---|
| 1172 | |
---|
| 1173 | return !error; |
---|
| 1174 | |
---|
| 1175 | } |
---|
| 1176 | |
---|
| 1177 | |
---|
| 1178 | size_t PS_1_4::getMachineInst( size_t Idx) |
---|
| 1179 | { |
---|
| 1180 | if (Idx < mPhase1TEX_mi.size()) { |
---|
| 1181 | return mPhase1TEX_mi[Idx]; |
---|
| 1182 | } |
---|
| 1183 | else { |
---|
| 1184 | Idx -= mPhase1TEX_mi.size(); |
---|
| 1185 | if (Idx < mPhase1ALU_mi.size()) { |
---|
| 1186 | return mPhase1ALU_mi[Idx]; |
---|
| 1187 | } |
---|
| 1188 | else { |
---|
| 1189 | Idx -= mPhase1ALU_mi.size(); |
---|
| 1190 | if (Idx < mPhase2TEX_mi.size()) { |
---|
| 1191 | return mPhase2TEX_mi[Idx]; |
---|
| 1192 | } |
---|
| 1193 | else { |
---|
| 1194 | Idx -= mPhase2TEX_mi.size(); |
---|
| 1195 | if (Idx < mPhase2ALU_mi.size()) { |
---|
| 1196 | return mPhase2ALU_mi[Idx]; |
---|
| 1197 | } |
---|
| 1198 | |
---|
| 1199 | } |
---|
| 1200 | |
---|
| 1201 | } |
---|
| 1202 | |
---|
| 1203 | } |
---|
| 1204 | |
---|
| 1205 | return 0; |
---|
| 1206 | |
---|
| 1207 | } |
---|
| 1208 | |
---|
| 1209 | |
---|
| 1210 | void PS_1_4::addMachineInst(const PhaseType phase, const uint inst) |
---|
| 1211 | { |
---|
| 1212 | switch(phase) { |
---|
| 1213 | |
---|
| 1214 | case ptPHASE1TEX: |
---|
| 1215 | mPhase1TEX_mi.push_back(inst); |
---|
| 1216 | break; |
---|
| 1217 | |
---|
| 1218 | case ptPHASE1ALU: |
---|
| 1219 | mPhase1ALU_mi.push_back(inst); |
---|
| 1220 | break; |
---|
| 1221 | |
---|
| 1222 | case ptPHASE2TEX: |
---|
| 1223 | mPhase2TEX_mi.push_back(inst); |
---|
| 1224 | |
---|
| 1225 | break; |
---|
| 1226 | |
---|
| 1227 | case ptPHASE2ALU: |
---|
| 1228 | mPhase2ALU_mi.push_back(inst); |
---|
| 1229 | break; |
---|
| 1230 | |
---|
| 1231 | |
---|
| 1232 | } // end switch(phase) |
---|
| 1233 | |
---|
| 1234 | } |
---|
| 1235 | |
---|
| 1236 | size_t PS_1_4::getMachineInstCount() |
---|
| 1237 | { |
---|
| 1238 | |
---|
| 1239 | return (mPhase1TEX_mi.size() + mPhase1ALU_mi.size() + mPhase2TEX_mi.size() + mPhase2ALU_mi.size()); |
---|
| 1240 | } |
---|
| 1241 | |
---|
| 1242 | |
---|
| 1243 | bool PS_1_4::bindAllMachineInstToFragmentShader() |
---|
| 1244 | { |
---|
| 1245 | bool passed; |
---|
| 1246 | |
---|
| 1247 | // there are 4 machine instruction ques to pass to the ATI fragment shader |
---|
| 1248 | passed = bindMachineInstInPassToFragmentShader(mPhase1TEX_mi); |
---|
| 1249 | passed &= bindMachineInstInPassToFragmentShader(mPhase1ALU_mi); |
---|
| 1250 | passed &= bindMachineInstInPassToFragmentShader(mPhase2TEX_mi); |
---|
| 1251 | passed &= bindMachineInstInPassToFragmentShader(mPhase2ALU_mi); |
---|
| 1252 | return passed; |
---|
| 1253 | |
---|
| 1254 | } |
---|
| 1255 | |
---|
| 1256 | |
---|
| 1257 | bool PS_1_4::expandMacro(const MacroRegModify & MacroMod) |
---|
| 1258 | { |
---|
| 1259 | |
---|
| 1260 | RegModOffset * regmod; |
---|
| 1261 | |
---|
| 1262 | // set source and destination registers in macro expansion |
---|
| 1263 | for (uint i = 0; i < MacroMod.RegModSize; i++) { |
---|
| 1264 | regmod = &MacroMod.RegMods[i]; |
---|
| 1265 | MacroMod.Macro[regmod->MacroOffset].mID = regmod->RegisterBase + mOpParrams[regmod->OpParramsIndex].Arg; |
---|
| 1266 | |
---|
| 1267 | } |
---|
| 1268 | |
---|
| 1269 | // turn macro support on so that ps.1.4 ALU instructions get put in phase 1 alu instruction sequence container |
---|
| 1270 | mMacroOn = true; |
---|
| 1271 | // pass macro tokens on to be turned into machine instructions |
---|
| 1272 | // expand macro to ps.1.4 by doing recursive call to doPass2 |
---|
| 1273 | bool passed = Pass2scan(MacroMod.Macro, MacroMod.MacroSize); |
---|
| 1274 | mMacroOn = false; |
---|
| 1275 | |
---|
| 1276 | return passed; |
---|
| 1277 | } |
---|
| 1278 | |
---|
| 1279 | |
---|
| 1280 | bool PS_1_4::BuildMachineInst() |
---|
| 1281 | { |
---|
| 1282 | |
---|
| 1283 | // check the states to see if a machine instruction can be assembled |
---|
| 1284 | |
---|
| 1285 | // assume all arguments have been set up |
---|
| 1286 | bool passed = false; |
---|
| 1287 | |
---|
| 1288 | |
---|
| 1289 | |
---|
| 1290 | passed = true; // assume everything will go okay untill proven otherwise |
---|
| 1291 | |
---|
| 1292 | // start with machine NOP instuction |
---|
| 1293 | // this is used after the switch to see if an instruction was set up |
---|
| 1294 | // determine which MachineInstID is required based on the op instruction |
---|
| 1295 | mOpType = mi_NOP; |
---|
| 1296 | |
---|
| 1297 | switch(mOpInst) { |
---|
| 1298 | // ALU operations |
---|
| 1299 | case sid_ADD: |
---|
| 1300 | case sid_SUB: |
---|
| 1301 | case sid_MUL: |
---|
| 1302 | case sid_MAD: |
---|
| 1303 | case sid_LRP: |
---|
| 1304 | case sid_MOV: |
---|
| 1305 | case sid_CMP: |
---|
| 1306 | case sid_CND: |
---|
| 1307 | case sid_DP2ADD: |
---|
| 1308 | case sid_DP3: |
---|
| 1309 | case sid_DP4: |
---|
| 1310 | mOpType = (MachineInstID)(mi_COLOROP1 + mArgCnt - 1); |
---|
| 1311 | |
---|
| 1312 | // if context is ps.1.x and Macro not on or a phase marker was found then put all ALU ops in phase 2 ALU container |
---|
| 1313 | if (((mActiveContexts & ckp_PS_1_1) && !mMacroOn) || mPhaseMarkerFound) mInstructionPhase = ptPHASE2ALU; |
---|
| 1314 | else mInstructionPhase = ptPHASE1ALU; |
---|
| 1315 | // check for alpha op in destination register which is OpParrams[0] |
---|
| 1316 | // if no Mask for destination then make it .rgba |
---|
| 1317 | if(mOpParrams[0].MaskRep == 0) mOpParrams[0].MaskRep = |
---|
| 1318 | GL_RED_BIT_ATI | GL_GREEN_BIT_ATI | GL_BLUE_BIT_ATI | ALPHA_BIT; |
---|
| 1319 | if (mOpParrams[0].MaskRep & ALPHA_BIT) { |
---|
| 1320 | mDo_Alpha = true; |
---|
| 1321 | mOpParrams[0].MaskRep -= ALPHA_BIT; |
---|
| 1322 | if(mOpParrams[0].MaskRep == 0) mOpType = mi_NOP; // only do alpha op |
---|
| 1323 | } |
---|
| 1324 | break; |
---|
| 1325 | |
---|
| 1326 | case sid_TEXCRD: |
---|
| 1327 | mOpType = mi_PASSTEXCOORD; |
---|
| 1328 | if (mPhaseMarkerFound) mInstructionPhase = ptPHASE2TEX; |
---|
| 1329 | else mInstructionPhase = ptPHASE1TEX; |
---|
| 1330 | break; |
---|
| 1331 | |
---|
| 1332 | case sid_TEXLD: |
---|
| 1333 | mOpType = mi_SAMPLEMAP; |
---|
| 1334 | if (mPhaseMarkerFound) mInstructionPhase = ptPHASE2TEX; |
---|
| 1335 | else mInstructionPhase = ptPHASE1TEX; |
---|
| 1336 | break; |
---|
| 1337 | |
---|
| 1338 | case sid_TEX: // PS_1_1 emulation |
---|
| 1339 | mOpType = mi_TEX; |
---|
| 1340 | mInstructionPhase = ptPHASE1TEX; |
---|
| 1341 | break; |
---|
| 1342 | |
---|
| 1343 | case sid_TEXCOORD: // PS_1_1 emulation |
---|
| 1344 | mOpType = mi_TEXCOORD; |
---|
| 1345 | mInstructionPhase = ptPHASE1TEX; |
---|
| 1346 | break; |
---|
| 1347 | |
---|
| 1348 | case sid_TEXREG2AR: |
---|
| 1349 | passed = expandMacro(texreg2ar_MacroMods); |
---|
| 1350 | break; |
---|
| 1351 | |
---|
| 1352 | case sid_TEXREG2GB: |
---|
| 1353 | passed = expandMacro(texreg2gb_MacroMods); |
---|
| 1354 | break; |
---|
| 1355 | |
---|
| 1356 | case sid_TEXDP3: |
---|
| 1357 | passed = expandMacro(texdp3_MacroMods); |
---|
| 1358 | break; |
---|
| 1359 | |
---|
| 1360 | case sid_TEXDP3TEX: |
---|
| 1361 | passed = expandMacro(texdp3tex_MacroMods); |
---|
| 1362 | break; |
---|
| 1363 | |
---|
| 1364 | case sid_TEXM3X2PAD: |
---|
| 1365 | passed = expandMacro(texm3x2pad_MacroMods); |
---|
| 1366 | break; |
---|
| 1367 | |
---|
| 1368 | case sid_TEXM3X2TEX: |
---|
| 1369 | passed = expandMacro(texm3x2tex_MacroMods); |
---|
| 1370 | break; |
---|
| 1371 | |
---|
| 1372 | case sid_TEXM3X3PAD: |
---|
| 1373 | // only 2 texm3x3pad instructions allowed |
---|
| 1374 | // use count to modify macro to select which mask to use |
---|
| 1375 | if(mTexm3x3padCount<2) { |
---|
| 1376 | texm3x3pad[4].mID = sid_R + mTexm3x3padCount; |
---|
| 1377 | mTexm3x3padCount++; |
---|
| 1378 | passed = expandMacro(texm3x3pad_MacroMods); |
---|
| 1379 | |
---|
| 1380 | } |
---|
| 1381 | else passed = false; |
---|
| 1382 | |
---|
| 1383 | break; |
---|
| 1384 | |
---|
| 1385 | case sid_TEXM3X3TEX: |
---|
| 1386 | passed = expandMacro(texm3x3tex_MacroMods); |
---|
| 1387 | break; |
---|
| 1388 | |
---|
| 1389 | case sid_DEF: |
---|
| 1390 | mOpType = mi_SETCONSTANTS; |
---|
| 1391 | mInstructionPhase = ptPHASE1TEX; |
---|
| 1392 | break; |
---|
| 1393 | |
---|
| 1394 | case sid_PHASE: // PS_1_4 only |
---|
| 1395 | mPhaseMarkerFound = true; |
---|
| 1396 | break; |
---|
| 1397 | |
---|
| 1398 | } // end of switch |
---|
| 1399 | |
---|
| 1400 | if(passed) passed = expandMachineInstruction(); |
---|
| 1401 | |
---|
| 1402 | return passed; |
---|
| 1403 | } |
---|
| 1404 | |
---|
| 1405 | |
---|
| 1406 | bool PS_1_4::expandMachineInstruction() |
---|
| 1407 | { |
---|
| 1408 | // now push instructions onto MachineInstructions container |
---|
| 1409 | // assume that an instruction will be expanded |
---|
| 1410 | bool passed = true; |
---|
| 1411 | |
---|
| 1412 | if (mOpType != mi_NOP) { |
---|
| 1413 | |
---|
| 1414 | // a machine instruction will be built |
---|
| 1415 | // this is currently the last one being built so keep track of it |
---|
| 1416 | if (mInstructionPhase == ptPHASE2ALU) { |
---|
| 1417 | mSecondLastInstructionPos = mLastInstructionPos; |
---|
| 1418 | mLastInstructionPos = mPhase2ALU_mi.size(); |
---|
| 1419 | } |
---|
| 1420 | |
---|
| 1421 | |
---|
| 1422 | switch (mOpType) { |
---|
| 1423 | case mi_COLOROP1: |
---|
| 1424 | case mi_COLOROP2: |
---|
| 1425 | case mi_COLOROP3: |
---|
| 1426 | { |
---|
| 1427 | addMachineInst(mInstructionPhase, mOpType); |
---|
| 1428 | addMachineInst(mInstructionPhase, mSymbolTypeLib[mOpInst].mPass2Data); |
---|
| 1429 | // send all parameters to machine inst container |
---|
| 1430 | for(int i=0; i<=mArgCnt; i++) { |
---|
| 1431 | addMachineInst(mInstructionPhase, mOpParrams[i].Arg); |
---|
| 1432 | addMachineInst(mInstructionPhase, mOpParrams[i].MaskRep); |
---|
| 1433 | addMachineInst(mInstructionPhase, mOpParrams[i].Mod); |
---|
| 1434 | // check if source register read is valid in this phase |
---|
| 1435 | passed &= isRegisterReadValid(mInstructionPhase, i); |
---|
| 1436 | } |
---|
| 1437 | |
---|
| 1438 | // record which registers were written to and in which phase |
---|
| 1439 | // mOpParrams[0].Arg is always the destination register r0 -> r5 |
---|
| 1440 | updateRegisterWriteState(mInstructionPhase); |
---|
| 1441 | |
---|
| 1442 | } |
---|
| 1443 | break; |
---|
| 1444 | |
---|
| 1445 | case mi_SETCONSTANTS: |
---|
| 1446 | addMachineInst(mInstructionPhase, mOpType); |
---|
| 1447 | addMachineInst(mInstructionPhase, mOpParrams[0].Arg); // dst |
---|
| 1448 | addMachineInst(mInstructionPhase, mConstantsPos); // index into constants array |
---|
| 1449 | break; |
---|
| 1450 | |
---|
| 1451 | case mi_PASSTEXCOORD: |
---|
| 1452 | case mi_SAMPLEMAP: |
---|
| 1453 | // if source is a temp register than place instruction in phase 2 Texture ops |
---|
| 1454 | if ((mOpParrams[1].Arg >= GL_REG_0_ATI) && (mOpParrams[1].Arg <= GL_REG_5_ATI)) { |
---|
| 1455 | mInstructionPhase = ptPHASE2TEX; |
---|
| 1456 | } |
---|
| 1457 | |
---|
| 1458 | addMachineInst(mInstructionPhase, mOpType); |
---|
| 1459 | addMachineInst(mInstructionPhase, mOpParrams[0].Arg); // dst |
---|
| 1460 | addMachineInst(mInstructionPhase, mOpParrams[1].Arg); // coord |
---|
| 1461 | addMachineInst(mInstructionPhase, mOpParrams[1].MaskRep + GL_SWIZZLE_STR_ATI); // swizzle |
---|
| 1462 | // record which registers were written to and in which phase |
---|
| 1463 | // mOpParrams[0].Arg is always the destination register r0 -> r5 |
---|
| 1464 | updateRegisterWriteState(mInstructionPhase); |
---|
| 1465 | break; |
---|
| 1466 | |
---|
| 1467 | case mi_TEX: // PS_1_1 emulation - turn CISC into RISC - phase 1 |
---|
| 1468 | addMachineInst(mInstructionPhase, mi_SAMPLEMAP); |
---|
| 1469 | addMachineInst(mInstructionPhase, mOpParrams[0].Arg); // dst |
---|
| 1470 | // tex tx becomes texld rx, tx with x: 0 - 3 |
---|
| 1471 | addMachineInst(mInstructionPhase, mOpParrams[0].Arg - GL_REG_0_ATI + GL_TEXTURE0_ARB); // interp |
---|
| 1472 | // default to str which fills rgb of destination register |
---|
| 1473 | addMachineInst(mInstructionPhase, GL_SWIZZLE_STR_ATI); // swizzle |
---|
| 1474 | // record which registers were written to and in which phase |
---|
| 1475 | // mOpParrams[0].Arg is always the destination register r0 -> r5 |
---|
| 1476 | updateRegisterWriteState(mInstructionPhase); |
---|
| 1477 | break; |
---|
| 1478 | |
---|
| 1479 | case mi_TEXCOORD: // PS_1_1 emulation - turn CISC into RISC - phase 1 |
---|
| 1480 | addMachineInst(mInstructionPhase, mi_PASSTEXCOORD); |
---|
| 1481 | addMachineInst(mInstructionPhase, mOpParrams[0].Arg); // dst |
---|
| 1482 | // texcoord tx becomes texcrd rx, tx with x: 0 - 3 |
---|
| 1483 | addMachineInst(mInstructionPhase, mOpParrams[0].Arg - GL_REG_0_ATI + GL_TEXTURE0_ARB); // interp |
---|
| 1484 | // default to str which fills rgb of destination register |
---|
| 1485 | addMachineInst(mInstructionPhase, GL_SWIZZLE_STR_ATI); // swizzle |
---|
| 1486 | // record which registers were written to and in which phase |
---|
| 1487 | // mOpParrams[0].Arg is always the destination register r0 -> r5 |
---|
| 1488 | updateRegisterWriteState(mInstructionPhase); |
---|
| 1489 | break; |
---|
| 1490 | |
---|
| 1491 | |
---|
| 1492 | |
---|
| 1493 | |
---|
| 1494 | } // end of switch (mOpType) |
---|
| 1495 | } // end of if (mOpType != mi_NOP) |
---|
| 1496 | |
---|
| 1497 | if(mDo_Alpha) { |
---|
| 1498 | // process alpha channel |
---|
| 1499 | // |
---|
| 1500 | // a scaler machine instruction will be built |
---|
| 1501 | // this is currently the last one being built so keep track of it |
---|
| 1502 | if (mInstructionPhase == ptPHASE2ALU) { |
---|
| 1503 | mSecondLastInstructionPos = mLastInstructionPos; |
---|
| 1504 | mLastInstructionPos = mPhase2ALU_mi.size(); |
---|
| 1505 | } |
---|
| 1506 | |
---|
| 1507 | MachineInstID alphaoptype = (MachineInstID)(mi_ALPHAOP1 + mArgCnt - 1); |
---|
| 1508 | addMachineInst(mInstructionPhase, alphaoptype); |
---|
| 1509 | addMachineInst(mInstructionPhase, mSymbolTypeLib[mOpInst].mPass2Data); |
---|
| 1510 | // put all parameters in instruction que |
---|
| 1511 | for(int i=0; i<=mArgCnt; i++) { |
---|
| 1512 | addMachineInst(mInstructionPhase, mOpParrams[i].Arg); |
---|
| 1513 | // destination parameter has no mask since it is the alpha channel |
---|
| 1514 | // don't push mask for parrameter 0 (dst) |
---|
| 1515 | if(i>0) addMachineInst(mInstructionPhase, mOpParrams[i].MaskRep); |
---|
| 1516 | addMachineInst(mInstructionPhase, mOpParrams[i].Mod); |
---|
| 1517 | // check if source register read is valid in this phase |
---|
| 1518 | passed &= isRegisterReadValid(mInstructionPhase, i); |
---|
| 1519 | } |
---|
| 1520 | |
---|
| 1521 | updateRegisterWriteState(mInstructionPhase); |
---|
| 1522 | } |
---|
| 1523 | |
---|
| 1524 | // instruction passed on to machine instruction so clear the pipe |
---|
| 1525 | clearMachineInstState(); |
---|
| 1526 | |
---|
| 1527 | return passed; |
---|
| 1528 | |
---|
| 1529 | } |
---|
| 1530 | |
---|
| 1531 | |
---|
| 1532 | void PS_1_4::updateRegisterWriteState(const PhaseType phase) |
---|
| 1533 | { |
---|
| 1534 | int reg_offset = mOpParrams[0].Arg - GL_REG_0_ATI; |
---|
| 1535 | |
---|
| 1536 | switch(phase) { |
---|
| 1537 | |
---|
| 1538 | case ptPHASE1TEX: |
---|
| 1539 | case ptPHASE1ALU: |
---|
| 1540 | Phase_RegisterUsage[reg_offset].Phase1Write = true; |
---|
| 1541 | break; |
---|
| 1542 | |
---|
| 1543 | case ptPHASE2TEX: |
---|
| 1544 | case ptPHASE2ALU: |
---|
| 1545 | Phase_RegisterUsage[reg_offset].Phase2Write = true; |
---|
| 1546 | break; |
---|
| 1547 | |
---|
| 1548 | } // end switch(phase) |
---|
| 1549 | |
---|
| 1550 | } |
---|
| 1551 | |
---|
| 1552 | |
---|
| 1553 | bool PS_1_4::isRegisterReadValid(const PhaseType phase, const int param) |
---|
| 1554 | { |
---|
| 1555 | bool passed = true; // assume everything will go alright |
---|
| 1556 | // if in phase 2 ALU and argument is a source |
---|
| 1557 | if((phase == ptPHASE2ALU) && (param>0)) { |
---|
| 1558 | // is source argument a temp register r0 - r5? |
---|
| 1559 | if((mOpParrams[param].Arg >= GL_REG_0_ATI) && (mOpParrams[param].Arg <= GL_REG_5_ATI)) { |
---|
| 1560 | int reg_offset = mOpParrams[param].Arg - GL_REG_0_ATI; |
---|
| 1561 | // if register was not written to in phase 2 but was in phase 1 |
---|
| 1562 | if((Phase_RegisterUsage[reg_offset].Phase2Write == false) && Phase_RegisterUsage[reg_offset].Phase1Write) { |
---|
| 1563 | // only perform register pass if there are ALU instructions in phase 1 |
---|
| 1564 | |
---|
| 1565 | if(mPhase1ALU_mi.size() > 0) { |
---|
| 1566 | // build machine instructions for passing a register from phase 1 to phase 2 |
---|
| 1567 | // NB: only rgb components of register will get passed |
---|
| 1568 | |
---|
| 1569 | addMachineInst(ptPHASE2TEX, mi_PASSTEXCOORD); |
---|
| 1570 | addMachineInst(ptPHASE2TEX, mOpParrams[param].Arg); // dst |
---|
| 1571 | addMachineInst(ptPHASE2TEX, mOpParrams[param].Arg); // coord |
---|
| 1572 | addMachineInst(ptPHASE2TEX, GL_SWIZZLE_STR_ATI); // swizzle |
---|
| 1573 | // mark register as being written to |
---|
| 1574 | Phase_RegisterUsage[reg_offset].Phase2Write = true; |
---|
| 1575 | } |
---|
| 1576 | |
---|
| 1577 | } |
---|
| 1578 | // register can not be used because it has not been written to previously |
---|
| 1579 | else passed = false; |
---|
| 1580 | } |
---|
| 1581 | |
---|
| 1582 | } |
---|
| 1583 | |
---|
| 1584 | return passed; |
---|
| 1585 | |
---|
| 1586 | } |
---|
| 1587 | |
---|
| 1588 | |
---|
| 1589 | void PS_1_4::optimize() |
---|
| 1590 | { |
---|
| 1591 | // perform some optimizations on ps.1.1 machine instructions |
---|
| 1592 | if (mActiveContexts & ckp_PS_1_1) { |
---|
| 1593 | // need to check last few instructions to make sure r0 is set |
---|
| 1594 | // ps.1.1 emulation uses r4 for r0 so last couple of instructions will probably require |
---|
| 1595 | // changine destination register back to r0 |
---|
| 1596 | if (mLastInstructionPos < mPhase2ALU_mi.size()) { |
---|
| 1597 | // first argument at mLastInstructionPos + 2 is destination register for all ps.1.1 ALU instructions |
---|
| 1598 | mPhase2ALU_mi[mLastInstructionPos + 2] = GL_REG_0_ATI; |
---|
| 1599 | // if was an alpha op only then modify second last instruction destination register |
---|
| 1600 | if ((mPhase2ALU_mi[mLastInstructionPos] == mi_ALPHAOP1) || |
---|
| 1601 | (mPhase2ALU_mi[mLastInstructionPos] == mi_ALPHAOP2) || |
---|
| 1602 | (mPhase2ALU_mi[mLastInstructionPos] == mi_ALPHAOP3) |
---|
| 1603 | |
---|
| 1604 | ) { |
---|
| 1605 | |
---|
| 1606 | mPhase2ALU_mi[mSecondLastInstructionPos + 2] = GL_REG_0_ATI; |
---|
| 1607 | } |
---|
| 1608 | |
---|
| 1609 | }// end if (mLastInstructionPos < mMachineInstructions.size()) |
---|
| 1610 | |
---|
| 1611 | }// end if (mActiveContexts & ckp_PS_1_1) |
---|
| 1612 | |
---|
| 1613 | } |
---|
| 1614 | |
---|
| 1615 | |
---|
| 1616 | void PS_1_4::clearMachineInstState() |
---|
| 1617 | { |
---|
| 1618 | // set current Machine Instruction State to baseline |
---|
| 1619 | mOpType = mi_NOP; |
---|
| 1620 | mOpInst = sid_INVALID; |
---|
| 1621 | mDo_Alpha = false; |
---|
| 1622 | mArgCnt = 0; |
---|
| 1623 | |
---|
| 1624 | for(int i=0; i<MAXOPPARRAMS; i++) { |
---|
| 1625 | mOpParrams[i].Arg = GL_NONE; |
---|
| 1626 | mOpParrams[i].Filled = false; |
---|
| 1627 | mOpParrams[i].MaskRep = GL_NONE; |
---|
| 1628 | mOpParrams[i].Mod = GL_NONE; |
---|
| 1629 | } |
---|
| 1630 | |
---|
| 1631 | } |
---|
| 1632 | |
---|
| 1633 | |
---|
| 1634 | void PS_1_4::clearAllMachineInst() |
---|
| 1635 | { |
---|
| 1636 | |
---|
| 1637 | mPhase1TEX_mi.clear(); |
---|
| 1638 | mPhase1ALU_mi.clear(); |
---|
| 1639 | mPhase2TEX_mi.clear(); |
---|
| 1640 | mPhase2ALU_mi.clear(); |
---|
| 1641 | |
---|
| 1642 | // reset write state for all registers |
---|
| 1643 | for(int i = 0; i<6; i++) { |
---|
| 1644 | Phase_RegisterUsage[i].Phase1Write = false; |
---|
| 1645 | Phase_RegisterUsage[i].Phase2Write = false; |
---|
| 1646 | |
---|
| 1647 | } |
---|
| 1648 | |
---|
| 1649 | mPhaseMarkerFound = false; |
---|
| 1650 | mConstantsPos = -4; |
---|
| 1651 | // keep track of the last instruction built |
---|
| 1652 | // this info is used at the end of pass 2 to optimize the machine code |
---|
| 1653 | mLastInstructionPos = 0; |
---|
| 1654 | mSecondLastInstructionPos = 0; |
---|
| 1655 | |
---|
| 1656 | mMacroOn = false; // macro's off at the beginning |
---|
| 1657 | mTexm3x3padCount = 0; |
---|
| 1658 | |
---|
| 1659 | } |
---|
| 1660 | |
---|
| 1661 | bool PS_1_4::doPass2() |
---|
| 1662 | { |
---|
| 1663 | clearAllMachineInst(); |
---|
| 1664 | // if pass 2 was successful, optimize the machine instructions |
---|
| 1665 | bool passed = Pass2scan(&mTokenInstructions[0], mTokenInstructions.size()); |
---|
| 1666 | if (passed) optimize(); |
---|
| 1667 | |
---|
| 1668 | return passed; |
---|
| 1669 | |
---|
| 1670 | } |
---|
| 1671 | |
---|
| 1672 | |
---|
| 1673 | bool PS_1_4::Pass2scan(const TokenInst * Tokens, const size_t size) |
---|
| 1674 | { |
---|
| 1675 | |
---|
| 1676 | // execute TokenInstructions to build MachineInstructions |
---|
| 1677 | bool passed = true; |
---|
| 1678 | SymbolDef* cursymboldef; |
---|
| 1679 | uint ActiveNTTRuleID; |
---|
| 1680 | |
---|
| 1681 | clearMachineInstState(); |
---|
| 1682 | |
---|
| 1683 | |
---|
| 1684 | // iterate through all the tokens and build machine instruction |
---|
| 1685 | // for each machine instruction need: optype, opinst, and up to 5 parameters |
---|
| 1686 | for(uint i = 0; i < size; i++) { |
---|
| 1687 | // lookup instruction type in library |
---|
| 1688 | |
---|
| 1689 | cursymboldef = &mSymbolTypeLib[Tokens[i].mID]; |
---|
| 1690 | ActiveNTTRuleID = Tokens[i].mNTTRuleID; |
---|
| 1691 | mCurrentLine = Tokens[i].mLine; |
---|
| 1692 | mCharPos = Tokens[i].mPos; |
---|
| 1693 | |
---|
| 1694 | switch(ActiveNTTRuleID) { |
---|
| 1695 | |
---|
| 1696 | case sid_CONSTANT: |
---|
| 1697 | case sid_COLOR: |
---|
| 1698 | case sid_REG_PS1_4: |
---|
| 1699 | case sid_TEX_PS1_4: |
---|
| 1700 | case sid_REG_PS1_1_3: |
---|
| 1701 | case sid_TEX_PS1_1_3: |
---|
| 1702 | // registars can be used for read and write so they can be used for dst and arg |
---|
| 1703 | passed = setOpParram(cursymboldef); |
---|
| 1704 | break; |
---|
| 1705 | |
---|
| 1706 | |
---|
| 1707 | case sid_DEFCONST: |
---|
| 1708 | case sid_UNARYOP: |
---|
| 1709 | case sid_BINARYOP: |
---|
| 1710 | case sid_TERNARYOP: |
---|
| 1711 | case sid_TEXOP_PS1_1_3: |
---|
| 1712 | case sid_TEXOP_PS1_4: |
---|
| 1713 | case sid_PHASEMARKER: |
---|
| 1714 | case sid_TEXCISCOP_PS1_1_3: |
---|
| 1715 | // if the last instruction has not been passed on then do it now |
---|
| 1716 | // make sure the pipe is clear for a new instruction |
---|
| 1717 | BuildMachineInst(); |
---|
| 1718 | if(mOpInst == sid_INVALID) { |
---|
| 1719 | mOpInst = cursymboldef->mID; |
---|
| 1720 | } |
---|
| 1721 | else passed = false; |
---|
| 1722 | break; |
---|
| 1723 | |
---|
| 1724 | case sid_DSTMASK: |
---|
| 1725 | case sid_SRCREP: |
---|
| 1726 | case sid_TEXSWIZZLE: |
---|
| 1727 | // could be a dst mask or a arg replicator |
---|
| 1728 | // if dst mask and alpha included then make up a alpha instruction: maybe best to wait until instruction args completed |
---|
| 1729 | mOpParrams[mArgCnt].MaskRep = cursymboldef->mPass2Data; |
---|
| 1730 | break; |
---|
| 1731 | |
---|
| 1732 | case sid_DSTMOD: |
---|
| 1733 | case sid_DSTSAT: |
---|
| 1734 | case sid_PRESRCMOD: |
---|
| 1735 | case sid_POSTSRCMOD: |
---|
| 1736 | mOpParrams[mArgCnt].Mod |= cursymboldef->mPass2Data; |
---|
| 1737 | break; |
---|
| 1738 | |
---|
| 1739 | |
---|
| 1740 | case sid_NUMVAL: |
---|
| 1741 | passed = setOpParram(cursymboldef); |
---|
| 1742 | // keep track of how many values are used |
---|
| 1743 | // update Constants array position |
---|
| 1744 | mConstantsPos++; |
---|
| 1745 | break; |
---|
| 1746 | |
---|
| 1747 | case sid_SEPERATOR: |
---|
| 1748 | mArgCnt++; |
---|
| 1749 | break; |
---|
| 1750 | } // end of switch |
---|
| 1751 | |
---|
| 1752 | if(!passed) break; |
---|
| 1753 | }// end of for: i<TokenInstCnt |
---|
| 1754 | |
---|
| 1755 | // check to see if there is still an instruction left in the pipe |
---|
| 1756 | if(passed) { |
---|
| 1757 | BuildMachineInst(); |
---|
| 1758 | // if there are no more instructions in the pipe than OpInst should be invalid |
---|
| 1759 | if(mOpInst != sid_INVALID) passed = false; |
---|
| 1760 | } |
---|
| 1761 | |
---|
| 1762 | |
---|
| 1763 | return passed; |
---|
| 1764 | } |
---|
| 1765 | |
---|
| 1766 | |
---|
| 1767 | |
---|
| 1768 | bool PS_1_4::setOpParram(const SymbolDef* symboldef) |
---|
| 1769 | { |
---|
| 1770 | bool success = true; |
---|
| 1771 | if(mArgCnt<MAXOPPARRAMS) { |
---|
| 1772 | if(mOpParrams[mArgCnt].Filled) mArgCnt++; |
---|
| 1773 | } |
---|
| 1774 | if (mArgCnt<MAXOPPARRAMS) { |
---|
| 1775 | mOpParrams[mArgCnt].Filled = true; |
---|
| 1776 | mOpParrams[mArgCnt].Arg = symboldef->mPass2Data; |
---|
| 1777 | } |
---|
| 1778 | else success = false; |
---|
| 1779 | |
---|
| 1780 | return success; |
---|
| 1781 | } |
---|
| 1782 | |
---|
| 1783 | |
---|
| 1784 | |
---|
| 1785 | |
---|
| 1786 | // ********************************************************************************* |
---|
| 1787 | // this is where the tests are carried out to make sure the PS_1_4 compiler works |
---|
| 1788 | |
---|
| 1789 | #ifdef _DEBUG |
---|
| 1790 | // check the functionality of functions in PS_1_4: each test will print to the output file PASSED of FAILED |
---|
| 1791 | void PS_1_4::test() |
---|
| 1792 | { |
---|
| 1793 | |
---|
| 1794 | |
---|
| 1795 | struct test1result{ |
---|
| 1796 | char character; |
---|
| 1797 | int line; |
---|
| 1798 | }; |
---|
| 1799 | |
---|
| 1800 | struct testfloatresult{ |
---|
| 1801 | char *teststr; |
---|
| 1802 | float fvalue; |
---|
| 1803 | int charsize; |
---|
| 1804 | }; |
---|
| 1805 | |
---|
| 1806 | char TestStr1[] = " \n\r //c \n\r// test\n\r \t c - \n\r , e"; |
---|
| 1807 | test1result test1results[] = { |
---|
| 1808 | {'c', 4}, |
---|
| 1809 | {'-', 4}, |
---|
| 1810 | {',', 5}, |
---|
| 1811 | {'e', 5} |
---|
| 1812 | }; |
---|
| 1813 | |
---|
| 1814 | testfloatresult testfloatresults[] = { |
---|
| 1815 | {"1 test", 1.0f, 1}, |
---|
| 1816 | {"2.3f test", 2.3f, 3}, |
---|
| 1817 | {"-0.5 test", -0.5f, 4}, |
---|
| 1818 | {" 23.6 test", 23.6f, 5}, |
---|
| 1819 | {" -0.021 test", -0.021f, 8}, |
---|
| 1820 | {"12 test", 12.0f, 2}, |
---|
| 1821 | {"3test", 3.0f, 1} |
---|
| 1822 | }; |
---|
| 1823 | |
---|
| 1824 | |
---|
| 1825 | |
---|
| 1826 | SymbolID test3result[] = { sid_MOV, sid_COMMA, sid_MUL, sid_ADD, sid_NEGATE, sid_T0 |
---|
| 1827 | }; |
---|
| 1828 | |
---|
| 1829 | #define PART2INST 17 |
---|
| 1830 | char TestStr3[] = "mov r0,c1"; |
---|
| 1831 | char TestSymbols[] = "mov"; |
---|
| 1832 | char passed[] = "PASSED\n"; |
---|
| 1833 | char failed[] = "***** FAILED *****\n"; |
---|
| 1834 | |
---|
| 1835 | int resultID = 0; |
---|
| 1836 | |
---|
| 1837 | // loop variable used in for loops |
---|
| 1838 | int i; |
---|
| 1839 | fp = fopen("ASMTests.txt", "wt"); |
---|
| 1840 | |
---|
| 1841 | // ************************************************************** |
---|
| 1842 | // first test: see if positionToNextSymbol can find a valid Symbol |
---|
| 1843 | fprintf(fp, "Testing: positionToNextSymbol\n"); |
---|
| 1844 | |
---|
| 1845 | mSource = TestStr1; |
---|
| 1846 | mCharPos = 0; |
---|
| 1847 | mCurrentLine = 1; |
---|
| 1848 | mEndOfSource = (int)strlen(mSource); |
---|
| 1849 | while (positionToNextSymbol()) { |
---|
| 1850 | fprintf(fp," character found: [%c] Line:%d : " , mSource[mCharPos], mCurrentLine); |
---|
| 1851 | if( (mSource[mCharPos] == test1results[resultID].character) && (mCurrentLine==test1results[resultID].line)) fprintf(fp, passed); |
---|
| 1852 | else fprintf(fp, failed); |
---|
| 1853 | resultID++; |
---|
| 1854 | mCharPos++; |
---|
| 1855 | } |
---|
| 1856 | fprintf(fp, "finished testing: positionToNextSymbol\n"); |
---|
| 1857 | |
---|
| 1858 | |
---|
| 1859 | // ************************************************************** |
---|
| 1860 | // Second Test |
---|
| 1861 | // did the type lib get initialized properly with a default name index |
---|
| 1862 | fprintf(fp, "\nTesting: getTypeDefText\n"); |
---|
| 1863 | char* resultstr = getTypeDefText(sid_MOV); |
---|
| 1864 | fprintf(fp, " default name of mov is: [%s]: %s", resultstr, (strcmp("mov", resultstr)==0)?passed:failed); |
---|
| 1865 | fprintf(fp, "finished testing: getTypeDefText\n"); |
---|
| 1866 | |
---|
| 1867 | // ************************************************************** |
---|
| 1868 | // ************************************************************** |
---|
| 1869 | // fourth test - does isSymbol work correctly |
---|
| 1870 | fprintf(fp, "\nTesting: isSymbol\n"); |
---|
| 1871 | mSource = TestStr3; |
---|
| 1872 | mCharPos = 0; |
---|
| 1873 | fprintf(fp, " before: [%s]\n", mSource + mCharPos); |
---|
| 1874 | fprintf(fp, " symbol to find: [%s]\n", TestSymbols); |
---|
| 1875 | if(isSymbol(TestSymbols, resultID)) { |
---|
| 1876 | fprintf(fp, " after: [%s] : %s", mSource + resultID + 1, (mSource[resultID + 1] == 'r')? passed:failed); |
---|
| 1877 | } |
---|
| 1878 | else fprintf(fp, failed); |
---|
| 1879 | fprintf(fp," symbol size: %d\n", resultID); |
---|
| 1880 | fprintf(fp, "finished testing: isSymbol\n"); |
---|
| 1881 | |
---|
| 1882 | // ************************************************************** |
---|
| 1883 | fprintf(fp, "\nTesting: isFloatValue\n"); |
---|
| 1884 | float fvalue = 0; |
---|
| 1885 | int charsize = 0; |
---|
| 1886 | char teststrfloat1[] = "1 test"; |
---|
| 1887 | mCharPos = 0; |
---|
| 1888 | int testsize = ARRAYSIZE(testfloatresults); |
---|
| 1889 | for(i=0; i<testsize; i++) { |
---|
| 1890 | mSource = testfloatresults[i].teststr; |
---|
| 1891 | fprintf(fp, " test string [%s]\n", mSource); |
---|
| 1892 | isFloatValue(fvalue, charsize); |
---|
| 1893 | fprintf(fp, " value is: %f should be %f: %s", fvalue, testfloatresults[i].fvalue, (fvalue == testfloatresults[i].fvalue)?passed:failed); |
---|
| 1894 | fprintf(fp, " char size is: %d should be %d: %s", charsize, testfloatresults[i].charsize, (charsize == testfloatresults[i].charsize)?passed:failed); |
---|
| 1895 | } |
---|
| 1896 | |
---|
| 1897 | fprintf(fp, "finished testing: isFloatValue\n"); |
---|
| 1898 | |
---|
| 1899 | |
---|
| 1900 | // ************************************************************** |
---|
| 1901 | |
---|
| 1902 | // simple compile test: |
---|
| 1903 | char CompileTest1src[] = "ps.1.4\n"; |
---|
| 1904 | SymbolID CompileTest1result[] = {sid_PS_1_4}; |
---|
| 1905 | |
---|
| 1906 | testCompile("Basic PS_1_4", CompileTest1src, CompileTest1result, ARRAYSIZE(CompileTest1result)); |
---|
| 1907 | |
---|
| 1908 | // ************************************************************** |
---|
| 1909 | char CompileTest2src[] = "ps.1.1\n"; |
---|
| 1910 | SymbolID CompileTest2result[] = {sid_PS_1_1}; |
---|
| 1911 | |
---|
| 1912 | testCompile("Basic PS_1_1", CompileTest2src, CompileTest2result, ARRAYSIZE(CompileTest2result)); |
---|
| 1913 | |
---|
| 1914 | // ************************************************************** |
---|
| 1915 | char CompileTest3src[] = "ps.1.4\ndef c0, 1.0, 2.0, 3.0, 4.0\n"; |
---|
| 1916 | SymbolID CompileTest3result[] = {sid_PS_1_4, sid_DEF, sid_C0, sid_COMMA, sid_VALUE, sid_COMMA, |
---|
| 1917 | sid_VALUE, sid_COMMA, sid_VALUE, sid_COMMA, sid_VALUE}; |
---|
| 1918 | |
---|
| 1919 | testCompile("PS_1_4 with defines", CompileTest3src, CompileTest3result, ARRAYSIZE(CompileTest3result)); |
---|
| 1920 | |
---|
| 1921 | |
---|
| 1922 | // ************************************************************** |
---|
| 1923 | char CompileTest4src[] = "ps.1.4\n//test kkl \ndef c0, 1.0, 2.0, 3.0, 4.0\ndef c3, 1.0, 2.0, 3.0, 4.0\n"; |
---|
| 1924 | SymbolID CompileTest4result[] = {sid_PS_1_4, sid_DEF, sid_C0, sid_COMMA, sid_VALUE, sid_COMMA, |
---|
| 1925 | sid_VALUE, sid_COMMA, sid_VALUE, sid_COMMA, sid_VALUE,sid_DEF, sid_C3, sid_COMMA, sid_VALUE, sid_COMMA, |
---|
| 1926 | sid_VALUE, sid_COMMA, sid_VALUE, sid_COMMA, sid_VALUE}; |
---|
| 1927 | |
---|
| 1928 | testCompile("PS_1_4 with 2 defines", CompileTest4src, CompileTest4result, ARRAYSIZE(CompileTest4result)); |
---|
| 1929 | |
---|
| 1930 | // ************************************************************** |
---|
| 1931 | char CompileTest5src[] = "ps.1.4\ndef c0, 1.0, 2.0, 3.0, 4.0\n"; |
---|
| 1932 | SymbolID CompileTest5result[] = {sid_PS_1_4, sid_DEF, sid_C0, sid_COMMA, sid_VALUE, sid_COMMA, |
---|
| 1933 | sid_VALUE, sid_COMMA, sid_VALUE, sid_COMMA, sid_VALUE}; |
---|
| 1934 | GLuint CompileTest5MachinInstResults[] = {mi_SETCONSTANTS, GL_CON_0_ATI, 0}; |
---|
| 1935 | |
---|
| 1936 | testCompile("PS_1_4 with defines", CompileTest3src, CompileTest3result, ARRAYSIZE(CompileTest3result), CompileTest5MachinInstResults, ARRAYSIZE(CompileTest5MachinInstResults)); |
---|
| 1937 | // ************************************************************** |
---|
| 1938 | char CompileTest6Src[] = "ps.1.4\nmov r0.xzw, c1 \nmul r3, r2, c3"; |
---|
| 1939 | SymbolID CompileTest6result[] = {sid_PS_1_4, sid_MOV, sid_R0, sid_RBA, sid_COMMA, sid_C1, |
---|
| 1940 | sid_MUL, sid_R3, sid_COMMA, sid_R2, sid_COMMA, sid_C3}; |
---|
| 1941 | |
---|
| 1942 | testCompile("PS_1_4 ALU simple", CompileTest6Src, CompileTest6result, ARRAYSIZE(CompileTest6result)); |
---|
| 1943 | |
---|
| 1944 | // ************************************************************** |
---|
| 1945 | // test to see if PS_1_4 compile pass 2 generates the proper machine instructions |
---|
| 1946 | char CompileTest7Src[] = "ps.1.4\ndef c0,1.0,2.0,3.0,4.0\nmov_x8 r1,v0\nmov r0,r1.g"; |
---|
| 1947 | |
---|
| 1948 | SymbolID CompileTest7result[] = { |
---|
| 1949 | sid_PS_1_4, sid_DEF, sid_C0, sid_COMMA, sid_VALUE, sid_COMMA, |
---|
| 1950 | sid_VALUE, sid_COMMA, sid_VALUE, sid_COMMA, sid_VALUE, sid_MOV, sid_X8, sid_R1, sid_COMMA, |
---|
| 1951 | sid_V0, sid_MOV, sid_R0, sid_COMMA, sid_R1, sid_GGGG |
---|
| 1952 | }; |
---|
| 1953 | |
---|
| 1954 | GLuint CompileTest7MachinInstResults[] = { |
---|
| 1955 | mi_SETCONSTANTS, GL_CON_0_ATI, 0, |
---|
| 1956 | mi_COLOROP1, GL_MOV_ATI, GL_REG_1_ATI, RGB_BITS, GL_8X_BIT_ATI, GL_PRIMARY_COLOR_ARB, GL_NONE, GL_NONE, |
---|
| 1957 | mi_ALPHAOP1, GL_MOV_ATI, GL_REG_1_ATI, GL_8X_BIT_ATI, GL_PRIMARY_COLOR_ARB, GL_NONE, GL_NONE, |
---|
| 1958 | mi_COLOROP1, GL_MOV_ATI, GL_REG_0_ATI, RGB_BITS, GL_NONE,GL_REG_1_ATI, GL_GREEN, GL_NONE, |
---|
| 1959 | mi_ALPHAOP1, GL_MOV_ATI, GL_REG_0_ATI, GL_NONE, GL_REG_1_ATI, GL_GREEN, GL_NONE, |
---|
| 1960 | }; |
---|
| 1961 | |
---|
| 1962 | |
---|
| 1963 | testCompile("PS_1_4 ALU simple modifier", CompileTest7Src, CompileTest7result, ARRAYSIZE(CompileTest7result), CompileTest7MachinInstResults, ARRAYSIZE(CompileTest7MachinInstResults)); |
---|
| 1964 | |
---|
| 1965 | // ************************************************************** |
---|
| 1966 | // test to see if a PS_1_1 can be compiled - pass 1 and pass 2 are checked |
---|
| 1967 | |
---|
| 1968 | char TestStr5[] = "ps.1.1\ndef c0,1.0,2.0,3.0,4.0\ntex t0\n// test\ntex t1\ndp3 t0.rgb, t0_bx2, t1_bx2\n+ mov r0,1 - t0"; |
---|
| 1969 | |
---|
| 1970 | SymbolID test5result[] = { |
---|
| 1971 | sid_PS_1_1, sid_DEF, sid_C0, sid_COMMA, sid_VALUE, sid_COMMA, |
---|
| 1972 | sid_VALUE, sid_COMMA, sid_VALUE, sid_COMMA, sid_VALUE, sid_TEX, sid_1T0, sid_TEX, sid_1T1, |
---|
| 1973 | sid_DP3, sid_1T0, sid_RGB, sid_COMMA, sid_1T0, sid_BX2, sid_COMMA, sid_1T1, sid_BX2, |
---|
| 1974 | |
---|
| 1975 | sid_PLUS, sid_MOV, sid_1R0, sid_COMMA, sid_INVERT, sid_1T0 |
---|
| 1976 | }; |
---|
| 1977 | |
---|
| 1978 | GLuint test5MachinInstResults[] = { |
---|
| 1979 | mi_SETCONSTANTS, GL_CON_0_ATI, 0, mi_SAMPLEMAP, GL_REG_0_ATI, GL_TEXTURE0_ARB, GL_SWIZZLE_STR_ATI, mi_SAMPLEMAP, GL_REG_1_ATI, GL_TEXTURE1_ARB, GL_SWIZZLE_STR_ATI, |
---|
| 1980 | mi_COLOROP2, GL_DOT3_ATI, GL_REG_0_ATI, RGB_BITS, GL_NONE, GL_REG_0_ATI, GL_NONE, GL_2X_BIT_ATI | GL_BIAS_BIT_ATI, |
---|
| 1981 | GL_REG_1_ATI, GL_NONE, GL_2X_BIT_ATI | GL_BIAS_BIT_ATI, |
---|
| 1982 | mi_COLOROP1, GL_MOV_ATI, GL_REG_0_ATI, RGB_BITS, GL_NONE, GL_REG_0_ATI, GL_NONE, GL_COMP_BIT_ATI, mi_ALPHAOP1, GL_MOV_ATI, GL_REG_0_ATI, |
---|
| 1983 | GL_NONE, GL_REG_0_ATI, GL_NONE, GL_COMP_BIT_ATI, |
---|
| 1984 | }; |
---|
| 1985 | |
---|
| 1986 | |
---|
| 1987 | testCompile("PS_1_1 Texture simple", TestStr5, test5result, ARRAYSIZE(test5result), test5MachinInstResults, ARRAYSIZE(test5MachinInstResults)); |
---|
| 1988 | |
---|
| 1989 | |
---|
| 1990 | // ************************************************************** |
---|
| 1991 | // test to see if a PS_1_2 CISC instructions can be compiled - pass 1 and pass 2 are checked |
---|
| 1992 | |
---|
| 1993 | char TestStr6[] = "ps.1.2\ndef c0,1.0,2.0,3.0,4.0\ntex t0\n// test\ntexreg2ar t1, t0"; |
---|
| 1994 | |
---|
| 1995 | SymbolID test6result[] = { |
---|
| 1996 | sid_PS_1_2, sid_DEF, sid_C0, sid_COMMA, sid_VALUE, sid_COMMA, |
---|
| 1997 | sid_VALUE, sid_COMMA, sid_VALUE, sid_COMMA, sid_VALUE, |
---|
| 1998 | sid_TEX, sid_1T0, |
---|
| 1999 | sid_TEXREG2AR, sid_1T1, sid_COMMA, sid_1T0 |
---|
| 2000 | }; |
---|
| 2001 | |
---|
| 2002 | GLuint test6MachinInstResults[] = { |
---|
| 2003 | // def c0 |
---|
| 2004 | mi_SETCONSTANTS, GL_CON_0_ATI, 0, |
---|
| 2005 | // texld r0, t0.str |
---|
| 2006 | mi_SAMPLEMAP, GL_REG_0_ATI, GL_TEXTURE0_ARB, GL_SWIZZLE_STR_ATI, |
---|
| 2007 | // mov r1.r, r0.a |
---|
| 2008 | mi_COLOROP1, GL_MOV_ATI, GL_REG_1_ATI, GL_RED_BIT_ATI, GL_NONE, GL_REG_0_ATI, GL_ALPHA, GL_NONE, |
---|
| 2009 | // mov r1.g, r0.r |
---|
| 2010 | mi_COLOROP1, GL_MOV_ATI, GL_REG_1_ATI, GL_GREEN_BIT_ATI, GL_NONE, GL_REG_0_ATI, GL_RED, GL_NONE, |
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| 2011 | // texld r1, r1 |
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| 2012 | mi_SAMPLEMAP, GL_REG_1_ATI, GL_REG_1_ATI, GL_SWIZZLE_STR_ATI, |
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| 2013 | }; |
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| 2014 | |
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| 2015 | |
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| 2016 | testCompile("PS_1_2 CISC instructions", TestStr6, test6result, ARRAYSIZE(test6result), test6MachinInstResults, ARRAYSIZE(test6MachinInstResults)); |
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| 2017 | |
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| 2018 | // ************************************************************** |
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| 2019 | // test to see if a PS_1_4 two phase can be compiled - pass 1 and pass 2 are checked |
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| 2020 | |
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| 2021 | char TestStr7[] = "ps.1.4\ndef c0,1.0,2.0,3.0,4.0\ntexld r0, t0\n// test\nmul r0, r0, c0\nphase\ntexld r1, r0\nmul r0,r0,r1\n"; |
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| 2022 | |
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| 2023 | SymbolID test7result[] = { |
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| 2024 | sid_PS_1_4, |
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| 2025 | // def c0,1.0,2.0,3.0,4.0 |
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| 2026 | sid_DEF, sid_C0, sid_COMMA, sid_VALUE, sid_COMMA, sid_VALUE, sid_COMMA, sid_VALUE, sid_COMMA, sid_VALUE, |
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| 2027 | // texld r0, t0 |
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| 2028 | sid_TEXLD, sid_R0, sid_COMMA, sid_T0, |
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| 2029 | // mul r0, r0, c0 |
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| 2030 | sid_MUL, sid_R0, sid_COMMA, sid_R0, sid_COMMA, sid_C0, |
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| 2031 | // phase |
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| 2032 | sid_PHASE, |
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| 2033 | // texld r1, r0 |
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| 2034 | sid_TEXLD, sid_R1, sid_COMMA, sid_R0, |
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| 2035 | // mul r0, r0, r1 |
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| 2036 | sid_MUL, sid_R0, sid_COMMA, sid_R0, sid_COMMA, sid_R1, |
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| 2037 | |
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| 2038 | }; |
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| 2039 | |
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| 2040 | GLuint test7MachinInstResults[] = { |
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| 2041 | // def c0 |
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| 2042 | mi_SETCONSTANTS, GL_CON_0_ATI, 0, |
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| 2043 | // texld r0, t0.str |
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| 2044 | mi_SAMPLEMAP, GL_REG_0_ATI, GL_TEXTURE0_ARB, GL_SWIZZLE_STR_ATI, |
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| 2045 | // mul r0, r0, c0 |
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| 2046 | mi_COLOROP2, GL_MUL_ATI, GL_REG_0_ATI, RGB_BITS, GL_NONE, GL_REG_0_ATI, GL_NONE, GL_NONE, GL_CON_0_ATI, GL_NONE, GL_NONE, |
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| 2047 | mi_ALPHAOP2, GL_MUL_ATI, GL_REG_0_ATI, GL_NONE, GL_REG_0_ATI, GL_NONE, GL_NONE, GL_CON_0_ATI, GL_NONE, GL_NONE, |
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| 2048 | // phase |
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| 2049 | // texld r1, r0.str |
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| 2050 | mi_SAMPLEMAP, GL_REG_1_ATI, GL_REG_0_ATI, GL_SWIZZLE_STR_ATI, |
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| 2051 | // pass ro register |
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| 2052 | mi_PASSTEXCOORD, GL_REG_0_ATI, GL_REG_0_ATI, GL_SWIZZLE_STR_ATI, |
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| 2053 | // mul r0, r0, r1 |
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| 2054 | mi_COLOROP2, GL_MUL_ATI, GL_REG_0_ATI, RGB_BITS, GL_NONE, GL_REG_0_ATI, GL_NONE, GL_NONE, GL_REG_1_ATI, GL_NONE, GL_NONE, |
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| 2055 | // mul r0.a, r0 |
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| 2056 | mi_ALPHAOP2, GL_MUL_ATI, GL_REG_0_ATI, GL_NONE, GL_REG_0_ATI, GL_NONE, GL_NONE, GL_REG_1_ATI, GL_NONE, GL_NONE, |
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| 2057 | }; |
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| 2058 | |
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| 2059 | |
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| 2060 | testCompile("PS_1_4 texture complex : Phase - instructions", TestStr7, test7result, ARRAYSIZE(test7result), test7MachinInstResults, ARRAYSIZE(test7MachinInstResults)); |
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| 2061 | |
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| 2062 | |
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| 2063 | fclose(fp); |
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| 2064 | fp = NULL; |
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| 2065 | //reset contexts |
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| 2066 | |
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| 2067 | // ************************************************************** |
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| 2068 | } |
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| 2069 | |
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| 2070 | void PS_1_4::testCompile(char* testname, char* teststr, SymbolID* testresult, uint testresultsize, GLuint* MachinInstResults, uint MachinInstResultsSize) |
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| 2071 | { |
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| 2072 | |
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| 2073 | char passed[] = "PASSED\n"; |
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| 2074 | char failed[] = "***** FAILED ****\n"; |
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| 2075 | |
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| 2076 | setActiveContexts(ckp_PS_BASE); |
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| 2077 | |
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| 2078 | fprintf(fp, "\n*** TESTING: %s Compile: Check Pass 1 and 2\n", testname); |
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| 2079 | fprintf(fp, " source to compile:\n[\n%s\n]\n", teststr); |
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| 2080 | bool compiled = compile(teststr); |
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| 2081 | fprintf(fp, " Pass 1 Lines scaned: %d, Tokens produced: %d out of %d: %s", |
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| 2082 | mCurrentLine, mTokenInstructions.size(), testresultsize, |
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| 2083 | (mTokenInstructions.size() == (uint)testresultsize) ? passed : failed); |
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| 2084 | |
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| 2085 | fprintf(fp, "\n Validating Pass 1:\n"); |
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| 2086 | |
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| 2087 | fprintf(fp, "\n Tokens:\n"); |
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| 2088 | uint i; |
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| 2089 | for(i = 0; i<(mTokenInstructions.size()); i++) { |
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| 2090 | fprintf(fp," Token[%d] [%s] %d: [%s] %d: %s", i, getTypeDefText(mTokenInstructions[i].mID), |
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| 2091 | mTokenInstructions[i].mID, getTypeDefText(testresult[i]), testresult[i], |
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| 2092 | (mTokenInstructions[i].mID == (uint)testresult[i]) ? passed : failed); |
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| 2093 | } |
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| 2094 | |
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| 2095 | if(MachinInstResults != NULL) { |
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| 2096 | fprintf(fp, "\n Machine Instructions:\n"); |
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| 2097 | |
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| 2098 | fprintf(fp, " Pass 2 Machine Instructions generated: %d out of %d: %s", getMachineInstCount(), |
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| 2099 | MachinInstResultsSize, (getMachineInstCount() == MachinInstResultsSize) ? passed : failed); |
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| 2100 | |
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| 2101 | size_t MIcount = getMachineInstCount(); |
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| 2102 | |
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| 2103 | fprintf(fp, "\n Validating Pass 2:\n"); |
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| 2104 | for(i = 0; i<MIcount; i++) { |
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| 2105 | fprintf(fp," instruction[%d] = 0x%x : 0x%x : %s", i, getMachineInst(i), MachinInstResults[i], (getMachineInst(i) == MachinInstResults[i]) ? passed : failed); |
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| 2106 | } |
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| 2107 | |
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| 2108 | fprintf(fp, "\n Constants:\n"); |
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| 2109 | for(i=0; i<4; i++) { |
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| 2110 | fprintf(fp, " Constants[%d] = %f : %s", i, mConstants[i], (mConstants[i] == (1.0f+i)) ? passed : failed); |
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| 2111 | } |
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| 2112 | } |
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| 2113 | if(!compiled) fprintf(fp, failed); |
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| 2114 | |
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| 2115 | fprintf(fp, "\nfinished testing: %s Compile: Check Pass 2\n\n", testname); |
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| 2116 | |
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| 2117 | setActiveContexts(ckp_PS_BASE); |
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| 2118 | } |
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| 2119 | |
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| 2120 | void PS_1_4::testbinder() |
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| 2121 | { |
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| 2122 | FILE* fp; |
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| 2123 | char BindTestStr[] = "mov_x8 r0,v0"; |
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| 2124 | char passed[] = "PASSED\n"; |
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| 2125 | char failed[] = "FAILED\n"; |
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| 2126 | #define BinderInstCnt 8 |
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| 2127 | GLuint BindMachinInst[BinderInstCnt] = {mi_COLOROP1, GL_MOV_ATI, GL_REG_0_ATI, GL_NONE, GL_8X_BIT_ATI, |
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| 2128 | GL_PRIMARY_COLOR_ARB, GL_NONE, GL_NONE}; |
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| 2129 | |
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| 2130 | fp = fopen("ASMTests.txt", "at"); |
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| 2131 | fprintf(fp,"Testing: bindMachineInstToFragmentShader\n"); |
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| 2132 | // fill Machin instruction container with predefined code |
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| 2133 | clearAllMachineInst(); |
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| 2134 | for(int i=0; i<BinderInstCnt; i++) { |
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| 2135 | mPhase2ALU_mi.push_back(BindMachinInst[i]); |
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| 2136 | } |
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| 2137 | fprintf(fp,"bindMachineInstToFragmentShader succes: %s\n",bindAllMachineInstToFragmentShader()?passed:failed); |
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| 2138 | fprintf(fp,"finished testing: bindAllMachineInstToFragmentShader\n"); |
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| 2139 | fclose(fp); |
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| 2140 | } |
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| 2141 | |
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| 2142 | #endif |
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| 2143 | |
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| 2144 | |
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| 2145 | |
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